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ISSCC 2017Session 23 · DRAM, MRAM & DRAM INTERFACESMemory

An 8Gb 12Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications

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📋 论文概要

本文提出了一款8Gb容量、每引脚12Gb/s速率的GDDR5X DRAM,旨在以低成本实现高带宽性能。该设计解决了GDDR5在高性能应用中的带宽瓶颈问题,通过优化接口和电路实现了更高的数据传输速率。

💡 主要创新点

核心指标
8Gb容量, 12Gb/s/pin速率
重要性
发表年份
ISSCC 2017

🏷 关键词

GDDR5X高带宽DRAM成本高效

📄 原文摘要

Cristian Chetreanu1, Stefan Dietrich1, Fabien Funfrock1, Marcos Alvarez Gonzalez1, Thomas Hein1, Eugen Huber1, Daniel Lauber1, Milena Ivanov1, Maksim Kuzmenka1, Chris Mohr2, Francisco Emiliano Munoz1, Juan Ocon Garrido1, Swetha Padaraju1, Sven Piatkowski1, Jan Pottgiesser1, Peter Pfefferl1, Manfred Plan1, Jens Polney1, Stefan Rau1, Michael Richter1, Ronny Schneider1, Ralf Oliver Seitter1, Wolfgang Spirkl1, Marc Walter1, Jörg Weller1, Filippo Vitale1 Micron, Munich, Germany Micron, Allen, TX 1 2 Over the last years, GDDR5 has emerged as the dominant standard for applications requiring high system bandwidth like graphic cards and game consoles. However, GDDR5 data rates are saturating due to limitations in the clock frequency and column-access cycle time (tCCD). To reach the data rate of 9Gb/s/pin

👥 作者与机构

Martin Brox1, Mani Balakrishnan1, Martin Broschwitz1,

分类:Memory · 年份:ISSCC 2017