A 2.5GHz Injection-Locked ADPLL with 197fsrms Integrated Jitter and -65dBc Reference Spur Using Time-Division Dual Calibration

📋 论文概要

本文提出了一种采用时分双校准（TDDC）技术的2.5GHz注入锁定ADPLL，实现了197fsrms的集成抖动和-65dBc的参考杂散。通过伪差分4级环形振荡器、10位频率控制字和20位ΔΣ调制器提高分辨率，解决了注入锁定PLL的参考杂散和抖动问题。

💡 主要创新点

• 提出时分双校准（TDDC）技术，通过时域分离注入与校准周期，抑制参考杂散。
• 采用20位ΔΣ调制器提升频率和延迟分辨率，实现150fs/LSB的延迟校准步长。

🏷 关键词

📄 原文摘要

7.3 shows the implemented schematic of the TDDC. The ILO is based on a pseudo-differential 4-stage ring oscillator, whose frequency is controlled by the 10b FCW. The frequency resolution is 100kHz/LSB. The FEPMD controls the calibration delay in the digitally controlled delay line. The delay is controlled with the 5b path mismatch control word PCW with a delay resolution of 150fs/LSB. For precise calibration, 20b delta-sigma modulators (ΔΣ) are employed to enhance the effective frequency and delay resolution. The enable generator (EG) indicates whether the current cycle is an injection cycle or a free-running cycle in order to forward φERR to FERR or PERR, respectively. 2 A clock generator using an injection-locked oscillator (ILO) offers remarkable jitter

👥 作者与机构

Sungwoo Kim1, Han-Gon Ko1, Sung-Yong Cho1, Jinhyung Lee1,

Soyeong Shin1, Min-Seong Choo1, Hankyu Chi2, Deog-Kyoon Jeong1 Seoul National University, Seoul, Korea SK hynix, Icheon, Korea 1 Figure 29