Reconfigurable Clock Networks for Random Skew Mitigation from Subthreshold to Nominal Voltage

📋 论文概要

该论文提出了一种可重构时钟网络，通过在不同电压下调整时钟网络深度来缓解从亚阈值到标称电压范围内的随机时钟偏差，解决了传统时钟网络在宽电压范围内性能受限的问题。

💡 主要创新点

• 提出可重构时钟网络架构，根据工作电压动态调整时钟树深度，以平衡线延迟和门延迟的影响。
• 通过理论分析和实验验证，揭示了随机时钟偏差与电压和时钟网络深度的关系，并提出了相应的优化策略。

🏷 关键词

📄 原文摘要

Clock network optimization is substantially affected by the operating voltage VDD, as the clock skew is dominated by different mechanisms and has a different balance between wire and repeater delay at different VDD (Fig. 26.3.1). At abovethreshold VDD, deep clock networks with several levels of repeaters are needed to control the clock slope in wires [1]. At sub-threshold VDD, shallow networks are needed as the gate delay dominates, and the random clock skew approximately grows proportionally to the square root of the number of levels [2]. At such VDD, the skew of clock networks designed at above-threshold VDD is much larger than at the nominal voltage VDD,nom, thus assuring a reasonable skew budget across a wide range of VDD is challenging [1-3]. To date, clock skew at low VDD has been mitigated via moderately deep networks with long-channel LVT buffers [1], design methodologies [2], [4], and voltage-adaptive delay insertion across different clock

👥 作者与机构

Longyang Lin, Saurabh Jain, Massimo Alioto

National University of Singapore, Singapore, Singapore