A 13b 4GS/s Digitally Assisted Dynamic 3-Stage Asynchronous Pipelined-SAR ADC

📋 论文概要

本文提出了一种13位4GS/s的数字辅助动态三级异步流水线逐次逼近（SAR）ADC，解决了高速高精度ADC在功耗和线性度上的挑战。通过采用动态放大器和数字校准技术，在保持高采样率的同时实现了低功耗和高精度。

💡 主要创新点

• 采用动态放大器代替传统闭环MDAC，降低了功耗并提高了速度，同时通过数字辅助校准补偿非理想性。
• 设计了三阶级联的异步流水线SAR架构，每级采用数字校准，实现了13位分辨率与4GS/s采样率的结合。
• 引入了数字辅助动态技术，包括背景校准和自校准，有效减轻了工艺、电压和温度变化的影响。

🏷 关键词

📄 原文摘要

Conrado Mesadri1, Ali Boumaalif3, John Mcgrath3, Umanath Kamath1, Ronnie De Le Torre1, Alvin Manlapat1, Daire Breathnach3, Christophe Erdmann1, Brendan Farley1 Xilinx, Dublin, Ireland Xilinx, San Jose, CA 3 Xilinx, Cork, Ireland 1 2 In recent years, the need for high performance RF sampling ADCs has driven impressive developments of pipelined-SAR and pipelined ADCs, all supported by time-interleaving [1-4]. All these designs use a closed loop MDAC amplifier in the first stage and digital calibration/equalization to alleviate finite gain, settling and memory effects, but the closed-loop amplifier remains a scaling bottleneck. In this work, a three-stage asynchronous pipelined-SAR with open-loop integratorbased amplifiers is used to maximize the sampling frequency, resolution and linearity. The solution is mostly supported by dynamic circuits and multiple calibration loops to reduce cost, power and noise, maximize process portability

👥 作者与机构

Bruno Vaz1, Adrian Lynam1, Bob Verbruggen1, Asma Laraba2,