A 22.5-to-32Gb/s 3.2pJ/b Referenceless Baud-Rate Digital CDR with DFE and CTLE in 28nm CMOS

📋 论文概要

本文提出了一种22.5-32Gb/s的无参考时钟波特率数字CDR，集成了DFE和CTLE，在28nm CMOS工艺中实现3.2pJ/b的低功耗。解决了传统波特率CDR需要外部参考时钟的问题，降低了系统复杂度。

💡 主要创新点

• 首次实现了无需参考时钟的波特率CDR，通过频率检测器实现宽捕获范围。
• 集成了DFE和CTLE，在高速率下保持低功耗（3.2pJ/b）。
• 采用全数字架构，减少了前端比较器和时钟分布网络。

🏷 关键词

📄 原文摘要

circuits (CDRs) are becoming more prevalent in high-speed receiver designs as they offer lower power consumption by sampling the received data only once per UI [1,2]. This reduces the number of front-end comparators and clock distribution networks [1]. However, current baud-rate CDRs require an external reference clock [1,2], adding to the system complexity in pin count and clock generation. While frequency detectors (FDs) allow CDR designs to operate without a reference clock and across a wide capture range [3-5], current FDs are not designed for baud-rate CDRs. As well, current FDs rely on sharp data edges and are not designed for significant ISI caused by channel loss at high data rates [3-5]. This work presents a reference-less baudrate CDR that operates from 22.5Gb/s to 32Gb/s with channel loss up to -14.8dB

👥 作者与机构

Wahid Rahman1, Danny Yoo1, Joshua Liang1, Ali Sheikholeslami1,

Hirotaka Tamura2, Takayuki Shibasaki2, Hisakatsu Yamaguchi2 University of Toronto, Toronto, Canada Fujitsu Laboratories, Kawasaki, Japan 1 2 Baud-rate clock and data recovery