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本文设计了一款64Gb/s PAM-4发射机，采用4抽头前馈均衡(FFE)解决高速PAM-4调制下的线性度挑战，实现了2.26pJ/b的能效，采用28nm CMOS FDSOI工艺。
Walter Audoglio1, Augusto Andrea Rossi1, Simone Erba1, Matteo Bassi2, Andrea Mazzanti2 STMicroelectronics, Pavia, Italy University of Pavia, Pavia, Italy 1 2 Electrical link migration requires serial interfaces to operate at increasing data rates. Despite the fact that most standards still employ NRZ, practical signal integrity constraints demand PAM-4 modulation, especially for some interconnect applications and low-loss profiles [1]. Nevertheless, compared to NRZ, the design of high-speed PAM-4 transmitters entails several challenges. Achieving high linearity without reducing the output amplitude is key to preserve high SNR, which is tightened by the intrinsic 1/3 eye amplitude reduction. Moreover, transitions between non-adjacent levels reduce horizontal eye openings, demanding wide bandwidth and tight timing constraints. In light of the above issues, pushing the transmitter to high data-rates while maintaining signal integrity and energy
Giovanni Steffan1, Emanuele Depaoli1, Enrico Monaco1, Nicolo Sabatino1,