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ISSCC 2016Session 3 · ULTRA-HIGH-SPEED TRANSCEIVERSWireline I/O28nm CMOS

A 40/50/100Gb/s PAM-4 Ethernet Transceiver in 28nm CMOS

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📋 论文概要

本文实现了一款基于28nm CMOS工艺的40/50/100Gb/s PAM-4以太网收发器,解决了NRZ信令在超过50Gb/s时功率效率和性能下降的问题。通过采用PAM-4调制技术,在高速率下实现了更好的信道适应性和功耗优化。

💡 主要创新点

工艺节点
28nm CMOS
重要性
发表年份
ISSCC 2016

🏷 关键词

PAM-4以太网收发器28nm CMOS

📄 原文摘要

Arun Tiruvur1, Belal Helal1, Chang-Feng Loi2, Chris Jiang1, Halil Cirit1, Irene Quek2, Jamal Riani1, James Gorecki1, Jennifer Wu1, Jorge Pernillo1, Lawrence Tse1, Michael Le3, Mohammad Ranjbar1, Pui-Shan Wong1, Pulkit Khandelwal1, Rajesh Narayanan1, Ravindran Mohanavelu1, Sameer Herlekar1, Sudeep Bhoja1, Vlad Shvydun1 Inphi, Santa Clara, CA, Inphi, Singapore, Singapore, 3Inphi, Irvine, CA 1 2 High-speed signaling using NRZ has approached speeds above 50Gb/s where it is extremely difficult to maintain power efficiency and performance over a wide variety of channels and applications. PAM-4 is emerging as one way to increase throughput in such band-limited channels. Higher modulation formats help to address cost in optical systems by packing more bits/wavelength [1]. Strong momentum in standards to adopt PAM-4 reflects these significant trends in the industry. At the same time, migrating transceiver designs to current technology

👥 作者与机构

Karthik Gopalakrishnan1, Alan Ren1, Amber Tan1, Arash Farhood1,

分类:Wireline I/O · 年份:ISSCC 2016