ISSCC 2016
Session 1
Plenary
Moore’s Law: A Path Going Forward William M. Holt
1. Moore’s Law Guides the Semiconductor Industry Moore’s Law has served as the guiding principle for the semiconductor industry for 50 years. The societal impact brought about by continually increasing the capability, af
ISSCC 2016
Session 1
Plenary
Three Pillars Enabling the Internet of Everything:
Networks, and Automated Real-Time Insights Sophie V. Vandebroek Chief Technology Officer, Xerox Corporation, Norwalk, CT 1. Introduction When smart everyday objects, information-centric networks, and automated realtime i
ISSCC 2016
Session 1
Plenary
Evolution of 5G Mobile Technology Toward 2020 and Beyond Seizo Onoe
During the past few decades, mobile communications have significantly contributed to the economic and social development of both developed and developing countries. Today, mobile communications form an indispensable part
ISSCC 2016
Session 1
Plenary
The Road Ahead for Securely-Connected Cars Lars Reger
The car as we know it is evolving. Thirty years ago the majority of innovations in the car were focused on the engine or body design, now 90 percent of car innovation is in electronics. Today, a typical car contains $799
ISSCC 2016
Session 10
Wireline I/O
A Pin-Efficient 20.83Gb/s/wire 0.94pJ/bit Forwarded Clock CNRZ-5-Coded SerDes up to 12mm for MCM Packages in 28nm CMOS
Brian Holden1, Ali Hormati1, Peter Hunt2, Margaret Johnston1, John Keay2, Sergio Pesenti1, Richard Simpson2, David Stauffer1, Andrew Stewart2, Giuseppe Surace2, Armin Tajalli1, Omid Talebi Amiri1, Anton Tschank2, Roger U
ISSCC 2016
Session 10
Wireline I/O
A 38mW 40Gb/s 4-Lane Tri-Band PAM-4 / 16QAM Transceiver in 28nm CMOS for High-Speed Memory Interface
Jieqiong Du1, Po-Tsang Huang1,2, Sheau Jiung Lee1, Huan-Neng Chen3, Chewn-Pu Jou3, Fu-Lung Hsueh3, Mau-Chung Frank Chang1,2 University of California, Los Angeles, CA, National Chiao Tung University, Hsinchu, Taiwan, 3 TS
ISSCC 2016
Session 10
Wireline I/O
An Analog Front-End for 100BASE-T1 Automotive Ethernet in 28nm CMOS
Karthik Swaminathan2, Ramalingam Pandarinathan2, Ramesh Pasagadugula2, VamshiKrishna Yakkala2, Mostafa Hammad1, Karim Abdelhalim1, Kaijun Li1, Su Cui1, Jing Wang1, Ahmad Chini1, Mehmet Tazebay1, Suresh Venkatesan2, Derek
ISSCC 2016
Session 10
Wireline I/O
A 12Gb/s 0.9mW/Gb/s Wide-Bandwidth InjectionType CDR in 28nm CMOS with Reference-Free Frequency Capture
Jacob Wysocki2, Koki Uchino1, Yoshifumi Miyajima3, Yosuke Ueno1, Kenichi Maruko1, Zhiwei Zhou1, Hideyuki Matsumoto1, Hideyuki Suzuki1, Norio Shoji1 Sony, Tokyo, Japan, Mixed Signal Systems, Scotts Valley, CA, 3 Sony LSI
ISSCC 2016
Session 10
Wireline I/O
A Digital PLL with Feedforward Multi-Tone Spur Cancelation Loop Achieving <-73dBc Fractional Spur and <-110dBc Reference Spur in 65nm CMOS
A low-spur PLL is desirable for many applications since it avoides mixing unwanted blocker signals, prevents emission mask violations or minimizes jitter in the clock source. Internal spurs result from the nature of PLL
ISSCC 2016
Session 10
Wireline I/O
A 185fsrms-Integrated-Jitter and -245dB FOM PVT-Robust Ring-VCO-Based Injection-Locked Clock Multiplier with a Continuous FrequencyTracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector
An injection-locked clock multiplier (ILCM) is considered to be a promising solution that can generate low-jitter, high-frequency clocks, using a limited budget in terms of silicon area and power consumption. However, an
ISSCC 2016
Session 10
Wireline I/O
A 12-to-26GHz Fractional-N PLL with Dual Continuous Tuning LC-D/VCOs
key challenge in multiple applications, from high-data-rate I/O to reconfigurable radio and radar. Conventional wireline and wireless LC-VCO based PLLs can cover a large tuning range using multiple frequency bands [1, 2]
ISSCC 2016
Session 11
Sensors
Dual-MEMS-Resonator Temperature-to-Digital Converter with 40μK Resolution and FOM of 0.12pJK2
Kamran Souri1, Rajkumar Palwai1, Will Chen1, Sudhakar Pamarti3, Joseph C. Doll1, Nicholas Miller1, Carl Arft1, Sassan Tabatabaei1, Carl Sechen2, Aaron Partridge1, Vinod Menon1 SiTime, Sunnyvale, CA, 2University of Texas,
ISSCC 2016
Session 11
Sensors
3D Ultrasonic Fingerprint Sensor-on-a-Chip
Xiaoyue Jiang1, Martin Lim3, Xi Li1, Eldwin Ng3, Utkarsh Singhal1, Julius M. Tsai 3, David A. Horsley2, Bernhard E. Boser1 University of California, Berkeley, CA, University of California, Davis, CA, 3Invensense, San Jos
ISSCC 2016
Session 11
Sensors
A Hybrid Multipath CMOS Magnetic Sensor with 210μTrms Resolution and 3MHz Bandwidth for Contactless Current Sensing
CMOS Hall sensors are widely used as magnetic sensors due to their linearity and ease of integration [1-3]. Being essentially n-well resistors, their resolution is determined by thermal noise and so decreases with bandwi
ISSCC 2016
Session 11
Sensors
1650µm2 Thermal-Diffusivity Sensors with Inaccuracies Down to ±0.75°C in 40nm CMOS
Compact temperature sensors are widely used in SoCs to monitor on-chip temperature gradients and hot-spots, which are known to negatively impact reliability [1-4]. In this application, sensors must be able to accurately
ISSCC 2016
Session 11
Sensors
A 3.2×1.5×0.8mm3 240nA 1.25-to-5.5V 32kHzDTCXO RTC Module with an Overall Accuracy of ±1ppm and an All-Digital 0.1ppm Compensation-Resolution Scheme at 1Hz
still remains the most popular, cost effective, low power, accurate solution for low-power portable applications. Simple solutions with overall accuracies of a few 100ppm are based on the combination of a through-hole or
ISSCC 2016
Session 11
Sensors
A 100-TRX-Channel Configurable 85-to-385HzFrame-Rate Analog Front-End for Touch Controller with Highly Enhanced Noise Immunity of 20Vpp
tablet PCs and home appliances that have touch-screen panels (TSPs) larger than 10 inches. However, there are many sources of noise that affect touch detection, and some of these noise sources, such as charger noise, sig
ISSCC 2016
Session 11
Sensors
A Load-Aware Pre-Emphasis Column Driver with 27% Settling-Time Reduction in ±18% Panel-Load RC Delay Variation for 240Hz UHD Flat-Panel Displays
Korea 1 3 As the panel size and resolution of flat-panel displays grow, the one-horizontal (1-H) time, in which a column driver should program data voltage into a row of pixels, is reduced and becomes a main bottleneck t
ISSCC 2016
Session 11
Sensors
Chip-Scale Electro-Optical 3D FMCW Lidar with 8μm Ranging Precision
Tae Joon Seok1, Yasuhiro Matsui3, Ming C. Wu1, Bernhard E. Boser1 University of California, Berkeley, CA, 2EPFL, Lausanne, Switzerland, Finisar, Fremont, CA 1 3 Miniaturized 3D imaging systems with sub-mm precision are o
ISSCC 2016
Session 12
Power Management
A Rational-Conversion-Ratio Switched-Capacitor DC-DC Converter Using Negative-Output Feedback
Switched-capacitor (SC) DC-DC converters have several advantages over inductive DC-DC converters in that they are easily integrated on-chip and can scale to desired power levels, rendering themselves promising for integr
ISSCC 2016
Session 12
Power Management
A 94.6%-Efficiency Fully Integrated SwitchedCapacitor DC-DC Converter in Baseline 40nm CMOS Using Scalable Parasitic Charge Redistribution
In recent years, there has been an ever-increasing interest in monolithic power supplies. Integrating the power supply with the application has many direct benefits, including a reduction of the bill of materials and red
ISSCC 2016
Session 12
Power Management
A 2-Output Step-Up/Step-Down SwitchedCapacitor DC-DC Converter with 95.8% Peak Efficiency and 0.85-to-3.6V Input Voltage Range
Switched-capacitor (SC) DC-DC converters have gained attention based on their ability to offer a low-cost high-efficiency power conversion, and allow a thin and compact module packaging [1]. However, the SC DC-DC convert
ISSCC 2016
Session 12
Power Management
A 10mW Fully Integrated 2-to-13V-Input BuckBoost SC Converter with 81.5% Peak Efficiency
In recent years, significant progress has been made on switched-capacitor DC-DC converters as they enable fully integrated on-chip power management. New converter topologies overcame the fixed input-to-output voltage lim
ISSCC 2016
Session 12
Power Management
A 2MHz 12-to-100V 90%-Efficiency SelfBalancing ZVS Three-Level DC-DC Regulator with Constant-Frequency AOT V2 Control and 5ns ZVS Turn-On Delay
Wide input rails (12V to 100V) are common in today’s automotive and industrial systems. Miniaturized DC-DC voltage regulators (VRs), which can provide a lowvoltage regulated output from a wide input range and deliver a f
ISSCC 2016
Session 12
Power Management
Capacitor-Current-Sensor Calibration Technique and Application in a 4-Phase Buck Converter with Load-Transient Optimization
causes a large output voltage undershoot ΔVUS and long settling time ts if the transient responses are slow [1]. Since the output capacitor current ICo instantly reflects ΔIload, transient response optimization for minim
ISSCC 2016
Session 12
Power Management
A 96%-Efficiency and 0.5%-Current-CrossRegulation Single-Inductor Multiple FloatingOutput LED Driver with 24b Color Resolution
Nan Hua University, Hsinchu, Taiwan 1 The calibration process of the ACC technique is described by the flow chart in Fig. 12.7.3. When ACC detects that LEDs are all on, the output voltage is sensed and defined as VOt. Le
ISSCC 2016
Session 12
Power Management
Synchronized Floating Current Mirror for Maximum LED Utilization in Multiple-String Linear LED Drivers
High-voltage linear drivers for multiple-string LEDs have been widely used in general lighting due to their low cost, simplicity, low electromagnetic interference (EMI), and high reliability. However, in conventional mul
ISSCC 2016
Session 12
Power Management
A Flying-Domain DC-DC Converter Powering a Cortex-M0 Processor with 90.8% Efficiency
Modern SoC designs employed in battery-life-constrained mobile applications feature multiple power domains to dynamically scale power-performance tradeoffs in response to application demands. Since each power domain requ
ISSCC 2016
Session 13
Wireless
A 940MHz-Bandwidth 28.8µs-Period 8.9GHz Chirp Frequency Synthesizer PLL in 65nm CMOS for X-Band FMCW Radar Applications
1.3 shows the circuit implementation of the low-power PI used in the phase DAC. The PI stage consists of two complementary parts, each interpolating between the rising or falling edges of the two input clocks, respective
ISSCC 2016
Session 13
Wireless
A Ku-Band 260mW FMCW Synthetic Aperture Radar TRX with 1.48GHz BW in 65nm CMOS for Micro-UAVs
capabilities to acquire imagery during night and inclement weather is indispensable for remote sensing, traffic mapping, etc. Recent unmanned aerial vehicles (UAVs) have been miniaturized to <1m3, providing an inexpensiv
ISSCC 2016
Session 13
Wireless
A 56Gb/s W-Band CMOS Wireless Transceiver
Noriaki Nagashima1, Jun Emmei1, Masato Dome1, Hisashi Kato1, Jian Pang1, Yoichi Kawano2, Toshihide Suzuki2, Taisuke Iwai2, Yuuki Seo1, Kimsrun Lim1, Shinji Sato1, Li Ning1, Kengo Nakata1, Kenichi Okada1, Akira Matsuzawa1
ISSCC 2016
Session 13
Wireless
A Microwave Injection-Locking Outphasing Modulator with 30dB Dynamic Range and 22% System Efficiency in 45nm CMOS SOI
University of California, Santa Barbara, CA 1 2 High-capacity microwave systems demand high-efficiency transmit architectures that support complex waveforms with high peak-to-average-power-ratio (PAPR) modulation. The ou
ISSCC 2016
Session 13
Wireless
A 4-Antenna-Path Beamforming Transceiver for 60GHz Multi-Gb/s Communication in 28nm CMOS
Kristof Vaesen1, Davide Guermandi1, Vito Giannini1,3, Steven Brebels1, Fortunato Frazzica1, André Bourdoux1, Charlotte Soens1, Wim Van Thillo1, Piet Wambacq1,2 imec, Heverlee, Belgium, Vrije Universiteit Brussel, Brussel
ISSCC 2016
Session 13
Wireless
A 42Gb/s 60GHz CMOS Transceiver for IEEE 802.11ay
Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon, Shoutarou Maki, Bangan Liu, Yun Wang, Noriaki Nagashima, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa Tokyo Institute of Technology, Tokyo, Japan It is
ISSCC 2016
Session 13
Wireless
A 0.22mm2 CMOS Resistive Charge-Based Direct-Launch Digital Transmitter with -159dBc/Hz Out-of-Band Noise
communication systems is dominated by the tradeoff between cost and performance. While the former claims ever-smaller footprints and bill of materials (BOM), the latter comprises a stringent set of requirements regarding
ISSCC 2016
Session 14
Other
A 126.1mW Real-Time Natural UI/UX Processor with Embedded Deep-Learning Core for Low-Power Smart Glasses
substitute due to their ease of use and suitability for advanced applications, such as gaming and augmented reality (AR) [1-2]. Most current HMD systems suffer from: 1) a lack of rich user interfaces, 2) short battery li
ISSCC 2016
Session 14
AI / ML
A 502GOPS and 0.984mW Dual-Mode ADAS SoC with RNN-FIS Engine for Intention Prediction in Automotive Black-Box System
forward-collision warning, advanced emergency braking, adaptive cruise control, and lane-keeping assistance. Recently, automotive black boxes are installed in cars for tracking accidents or theft. In this paper, a dual-m
ISSCC 2016
Session 14
Other
A 0.55V 1.1mW Artificial-Intelligence Processor with PVT Compensation for Micro Robots
applications, such as unmanned delivery services. The robots, shown in Fig. 14.3.1, have enhanced controllers that realize AI functions, such as perception (information extraction) and cognition (decision making). Histor
ISSCC 2016
Session 14
Other
A 21.5M-Query-Vectors/s 3.37nJ/Vector Reconfigurable k-Nearest-Neighbor Accelerator with Adaptive Precision in 14nm Tri-Gate CMOS
Sudhir K. Satpathy, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy Intel, Hillsboro, OR Energy-efficient k-nearest-neighbor (kNN) computations are key building blocks for computer vision, classification, and machine-l
ISSCC 2016
Session 14
AI / ML
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
Nvidia, Westford, MA 1 2 Deep learning using convolutional neural networks (CNN) gives state-of-the-art accuracy on many computer vision tasks (e.g. object detection, recognition, segmentation). Convolutions account for
ISSCC 2016
Session 14
AI / ML
A 1.42TOPS/W Deep Convolutional Neural Network Recognition Processor for Intelligent IoE Systems
Internet-ofEverything (IoE) devices to data center servers for intelligent recognition processes is impractical for energy reasons, requiring in-situ processing of such data. However, algorithms accelerated by previous r
ISSCC 2016
Session 14
Other
A 4Gpixel/s 8/10b H.265/HEVC Video Decoder Chip for 8K Ultra HD Applications
Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto Waseda University, Kitakyushu, Japan 8K Ultra HD is being promoted as the next-generation digital video format. From a com
ISSCC 2016
Session 15
Data Converters
A 24.7mW 45MHz-BW 75.3dB-SNDR SARAssisted CT ΔΣ Modulator with 2nd-Order Noise Coupling in 65nm CMOS
Technology advancement has recently made it attractive to replace the flash quantizer (QTZ) in a multibit ΔΣ modulator by an asynchronous successiveapproximation-register (ASAR) QTZ to improve the overall power efficienc
ISSCC 2016
Session 15
Data Converters
A 2.2GHz Continuous-Time ΔΣ ADC with -102dBc THD and 25MHz BW
Shagun Bajoria1, Jan Niehof1, Robert Rutten1, Bert Oude-Essink2, Franco Fritschij2, Jagdip Singh2, Gerard Lassche2 NXP Semiconductors, Eindhoven, The Netherlands, Catena Microelectronics, Delft, The Netherlands 1 2 The t
ISSCC 2016
Session 15
Data Converters
A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣM
DEE, FCT, Universidade NOVA de Lisboa, Caparica, Portugal, CTS-UNINOVA, Caparica, Portugal 1 2 ΔΣM performance can be improved by using MASH or SMASH structures to obtain higher-order noise shaping [1]. They have better
ISSCC 2016
Session 15
Data Converters
A 280µW 24kHz-BW 98.5dB-SNDR Chopped Single-Bit CT ΔΣM Achieving <10Hz 1/f Noise Corner Without Chopping Artifacts
IIT Madras, Chennai, India Many industrial applications require high-resolution ADCs whose low-frequency performance is important. CTDSMs are attractive due to their implicit antialiasing and resistive inputs. However, t
ISSCC 2016
Session 15
Data Converters
A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS
Cambridge, MA 1 2 The width of RF bands commonly used for cellular telecommunications has grown from 35-to-75MHz for 2G/3G/4G platforms to 100-to-200MHz for today’s LTE, and the desire for relaxed image-rejection filteri
ISSCC 2016
Session 15
Data Converters
A 160MHz-BW 72dB-DR 40mW Continuous-Time ΔΣ Modulator in 16nm CMOS with Analog ISIReduction Technique
baseband ADC of an LTE-A receiver. To boost user throughput and increase network capacity, CT-DSMs will need to increase signal bandwidth (BW) while maintaining sufficient dynamic range (DR) and good power efficiency. Fo
ISSCC 2016
Session 15
Data Converters
A 1.65mW 0.16mm2 Dynamic Zoom-ADC with 107.5dB DR in 20kHz BW
stereo channels to achieve effective acoustic noise and echo cancellation, thus demanding ADCs with low power and minimal die area. Zoom-ADCs should be well suited for such applications, since they combine compact and en
ISSCC 2016
Session 15
Data Converters
A 22.3b 1kHz 12.7mW Switched-Capacitor ΔΣ Modulator with Stacked Split-Steering Amplifiers
West Silicon EURL, Hottot les Bagues, France 1 2 Efforts to improve the resolution and power-efficiency of ADCs continue unabated, as is well documented in [2]. Although the number of new switchedcapacitor (SC) ADC publi
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