A 12-to-26GHz Fractional-N PLL with Dual Continuous Tuning LC-D/VCOs

📋 论文概要

该论文提出了一种12至26GHz的分数-N锁相环，采用双连续调谐LC-D/VCO架构，解决了宽带PLL中频率调谐范围与相位噪声之间的权衡问题。通过双VCO的连续调谐，避免了传统多频带切换带来的校准复杂度和噪声退化。

💡 主要创新点

• 提出双连续调谐LC-D/VCO架构，实现12-26GHz的宽频率覆盖，无需频带切换校准。
• 采用分数-N锁相环设计，结合双VCO的连续调谐特性，在宽调谐范围内保持低相位噪声。

🏷 关键词

📄 原文摘要

key challenge in multiple applications, from high-data-rate I/O to reconfigurable radio and radar. Conventional wireline and wireless LC-VCO based PLLs can cover a large tuning range using multiple frequency bands [1, 2], typically using a calibration loop to select an operating band for the VCO, then allowing the PLL to lock within that band. In effect, the in-band frequency tuning range of a typical high-performance LC-VCO covers a small fraction of the total range, the remainder of which is covered using switched high-Q fixed capacitors. This approach has been favored first due to the typically inferior quality factor of analog varactors as compared to that of high-Q vertical natural capacitors (VNCs) with CMOS switches, and second due to the unacceptable noise sensitivity of the VCO control node if the tuning

👥 作者与机构

Mark Ferriss, Bodhisatwa Sadhu, Alexander Rylyakov,

Herschel Ainspan, Daniel Friedman IBM Research, Yorktown Heights, NY High-performance, flexible clock synthesis is a