iRazor: 3-Transistor Current-Based Error Detection and Correction in an ARM Cortex-R4 Processor

📋 论文概要

该论文提出了一种基于3晶体管电流的误差检测与纠正(EDAC)技术，并成功应用于ARM Cortex-R4处理器，旨在消除传统时序裕量带来的性能与功耗损失。通过电流模式检测关键路径时序违规，实现了低开销、高能效的错误修复。

💡 主要创新点

• 采用3晶体管电流检测替代传统电压或翻转检测，降低了面积和功耗开销。
• 在商用ARM Cortex-R4处理器上实现完整的EDAC系统，验证了实际应用中的有效性。
• 通过电流比较和反馈机制实现单周期错误恢复，避免了流水线刷新带来的性能损失。

🏷 关键词

📄 原文摘要

M. Alioto2, D. Blaauw1, D. Sylvester1 University of Michigan, Ann Arbor, MI, National University of Singapore, Singapore, Singapore 1 2 It is well known that technology scaling has led to increasing process/voltage/temperature/aging margins that substantially degrade performance and power in modern processors and SoCs. One approach to address these large timing margins is the use of specialized registers on critical paths that perform error detection and correction (EDAC) [1-5]. While promising, the previously proposed implementations have been limited in several ways. Most notably, they often incur large overheads beyond conventional register designs (e.g., 8-to-44 additional transistors per register). This becomes an obstacle for commercial designs and, hence, there have been no reported implementations of EDAC approaches within substantial commercial processors. Finally, the performance gain from EDAC approaches has not been thoroughly quantified in

👥 作者与机构

Y. Zhang1, M. Khayatzadeh1, K. Yang1, M. Saligane1, N. Pinckney1,