A 56Gb/s NRZ-Electrical 247mW/lane Serial-Link Transceiver in 28nm CMOS

📋 论文概要

该论文提出了一款56Gb/s NRZ串行链路收发器，采用28nm CMOS工艺，每通道功耗仅247mW，旨在满足数据中心对超过50Gb/s高速通信的需求，并提升功率效率。

💡 主要创新点

• 采用四分之一速率架构和半速率时钟数据恢复（CDR）电路，降低功耗并提高数据速率。
• 通过优化发射器输出级和接收器连续时间线性均衡器（CTLE），实现低功耗下的高信号完整性。

🏷 关键词

📄 原文摘要

Yasufumi Sakai1, Hiroki Miyaoka2, Futoshi Terasawa2, Masahiro Kudo2, Hideki Kano2, Atsushi Matsuda2, Shigeaki Kawai2, Tomoyuki Arai2, Hirohito Higashi2, Naoaki Naka2, Hisakatsu Yamaguchi1, Toshihiko Mori1, Yoichi Koyanagi1, Hirotaka Tamura1 Fujitsu Laboratories, Kawasaki, Japan, Socionext, Yokohama, Japan 1 2 With the rapid growth of data traffic in data centers, data rates over 50Gb/s/signal (e.g., OIF-CEI-56G-VSR) will eventually be required in wireline chip-to-module or chip-to-chip communications [1–3]. To achieve better power efficiency than that of existing 25Gb/s/signal designs, a high-speed yet energy-efficient front-end is needed in both the transmitter and receiver. A receiver front-end with baud-rate architecture [1] has been successfully operated at 56Gb/s, but additional components such as eye-monitoring comparators, phase detectors, and clock recovery circuitry as well as a power-efficient transmitter are needed to build a

👥 作者与机构

Takayuki Shibasaki1, Takumi Danjo1, Yuuki Ogata1,