A 0.0021mm2 1.82mW 2.2GHz PLL Using TimeBased Integral Control in 65nm CMOS

📋 论文概要

本文提出一种基于时间积分控制的2.2GHz锁相环（PLL），采用65nm CMOS工艺，面积仅0.0021mm²，功耗1.82mW。通过时间域积分替代传统大环路滤波器电容，解决了模拟电荷泵PLL面积大的问题。

💡 主要创新点

• 提出时间域积分控制（Time-Based Integral Control）技术，用数字时间转换器替代大电容实现环路滤波，大幅减小芯片面积。
• 在65nm CMOS下实现了0.0021mm²的超小面积PLL，同时保持低功耗（1.82mW）和2.2GHz的工作频率。

🏷 关键词

📄 原文摘要

generators in analog, digital, RF, and embedded systems to generate a high frequency output clock from a low frequency reference clock. Modern systems-on-chip (SoCs) require many such PLLs that cater to multi-core processors, memories, IO interfaces and power management. A ring-oscillator-based analog charge-pump PLL offers a flexible and power-efficient way to implement such clock multipliers. However, frequency compensation of analog PLLs requires a large loop filter capacitor that occupies significant area. The area penalty is further exacerbated in deep sub-micron CMOS processes due to increasing oscillator gain and gate leakage. For example, a 2GHz PLL in 65nm CMOS requires a 90pF capacitor (R=1kΩ) to achieve 10MHz bandwidth and 70° phase margin. Assuming a capacitor density of 1fF/μm2, a

👥 作者与机构

Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu,

Ahmed Elkholy, Seong-Joong Kim, Pavan Kumar Hanumolu University of Illinois, Urbana-Champaign, IL Phase-locked loops (PLLs) are de-facto clock