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本文提出了一种采用14nm FinFET工艺实现的30Gb/s接收数据路径，功耗仅0.8pJ/b，适用于短距离铜信道通信。该设计满足了CEI-28G-VSR标准对低功耗均衡器的需求，实现了低于1pJ/b的能效目标。
Marcel Kossel, Thomas Morf, Lukas Kull, Alessandro Cevrero, Hazar Yueksel, Ilter Oezkaya, Danny Luu, Thomas Toifl IBM Zurich Research Laboratory, Rüshlikon, Switzerland The demand for energy-efficient I/O link transceivers operating at raw data-rates in the tens of Gb/s continues to fuel innovation in the field of wireline communication [1]. Receiving equalizers under one pJ/b are sought for chip-to-chip and chip-to-module links designed to operate across short-reach copper channels. Standards such as CEI-28G-VSR suit chip-to-module communication at raw data rates up to 28Gb/s and 10-12dB insertion loss at Nyquist. Proprietary and open standards in the same speed range are being developed too for data and memory-centric systems co-designed with CPUs and GPUs and channels with insertion loss on the order of 20dB [2]. This work describes a receiver data-path implemented in 14nm FinFET SOI CMOS
Pier Andrea Francese, Matthias Brändli, Christian Menolfi,