A 0.35mW 12b 100MS/s SAR-Assisted Digital Slope ADC in 28nm CMOS Chun-Cheng Liu

📋 论文概要

本文提出了一种28nm CMOS工艺下的0.35mW 12位100MS/s SAR辅助数字斜坡ADC。针对高速SAR ADC中比较器噪声导致的功耗指数增长问题，该结构通过SAR粗量化与数字斜坡细量化结合，显著降低了比较器噪声对功耗的影响，实现了高能效模数转换。

💡 主要创新点

• 采用SAR粗量化和数字斜坡细量化混合架构，在保持高分辨率的同时大幅减少比较器噪声带来的功耗开销。
• 数字斜坡转换利用电容阵列和数字逻辑实现高线性度，避免了传统SAR中高功耗的精细比较器，整体功耗仅0.35mW。

🏷 关键词

📄 原文摘要

In recent years, the operation speed of SAR ADCs has improved with the scaling of CMOS technology. SAR ADCs achieve a few hundreds of MS/s with 8-to-10b resolution. The SNR of high-speed SAR ADCs is mainly dominated by comparator noise and usually limited to 50 to 60dB. The power consumption increases exponentially to suppress comparator noise in a limited comparison time to improve SNR. Noise-tolerant SAR ADCs [1] reduce comparator power in the first few bit cycles by using a coarse comparator. However, the fine comparator in the remaining bit cycles still consumes significant power to achieve an SNR greater than 60dB. SAR-assisted pipelined ADCs [2,3] do not require a low-noise comparator, but design restrictions in advanced CMOS processes make highperformance amplifier design challenging. Using a low-gain or a dynamic amplifier induces gain errors between stages. Besides, the amplifier and back-end stages

👥 作者与机构

MediaTek, Hsinchu, Taiwan