A 940MHz-Bandwidth 28.8µs-Period 8.9GHz Chirp Frequency Synthesizer PLL in 65nm CMOS for X-Band FMCW Radar Applications

📋 论文概要

本文提出了一种用于X波段FMCW雷达的940MHz带宽、28.8µs周期的8.9GHz chirp频率合成器PLL，采用65nm CMOS工艺实现。解决了宽带chirp信号快速生成和低功耗的问题，通过低功耗相位插值器设计避免了crowbar电流。

💡 主要创新点

• 采用互补双路相位插值器结构，通过固定电流分配实现5位温度计码控制的插值权重，无需消耗crowbar电流，降低功耗。
• 实现了940MHz带宽和28.8µs短周期的chirp信号合成，适用于高分辨率FMCW雷达应用。

🏷 关键词

📄 原文摘要

1.3 shows the circuit implementation of the low-power PI used in the phase DAC. The PI stage consists of two complementary parts, each interpolating between the rising or falling edges of the two input clocks, respectively [8]. The interpolation weight (α) is adjusted by a 5b thermometer-code, adjusting the allocation of a fixed current I0 between I1 and I2. The phase interpolation is performed when each of the two currents I1 and I2 starts charging a shared capacitance when the respective clock edge arrives. This PI design has an advantage in that it does not dissipate crowbar currents unlike the other PIs that rely on the contention between the two driving stages. 2 To obtain a 20cm-resolution image within a 15m distance using an X-band FMCW radar, an agile chirp frequency synthesizer phase-locked loop (FSPLL) with a wide

👥 作者与机构

Hwanseok Yeo1,2, Sigang Ryu1, Yoontaek Lee1, Seuk Son1, Jaeha Kim1

Seoul National University, Seoul, Korea, Samsung Semiconductor, Hwaseong, Korea 1 Figure 13