A 38mW 40Gb/s 4-Lane Tri-Band PAM-4 / 16QAM Transceiver in 28nm CMOS for High-Speed Memory Interface

📋 论文概要

提出一种三频带PAM-4/16QAM混合调制的4通道收发机，在28nm CMOS工艺下实现40Gb/s数据率且功耗仅38mW，旨在解决高速内存接口的带宽和能效瓶颈。

💡 主要创新点

• 采用三频带（Tri-Band）PAM-4与16QAM混合调制方案，在保持高频谱效率的同时降低功耗。
• 通过4通道并行架构和低功耗电路技术，实现40Gb/s总速率下仅38mW的超低功耗。
• 针对高速内存接口优化，支持多频带信号传输以提升信道容量和抗噪性。

🏷 关键词

📄 原文摘要

Jieqiong Du1, Po-Tsang Huang1,2, Sheau Jiung Lee1, Huan-Neng Chen3, Chewn-Pu Jou3, Fu-Lung Hsueh3, Mau-Chung Frank Chang1,2 University of California, Los Angeles, CA, National Chiao Tung University, Hsinchu, Taiwan, 3 TSMC, Hsinchu, Taiwan 1 2 The continuous scaling of CMOS technology increases processor performance and memory capacity, requiring the CPU/Memory interface to have ever-higher bandwidth and energy efficiency over the past few years. Among those cuttingedge interface technologies, multi-band (multi-tone) signaling has shown great potential because of its high data-rate capability along with its low energy consumption [3]-[5]. With spectrally divided signaling, the multi-band transceiver can be designed to avoid spectral notches with extended communication bandwidth of multi-drop buses [4]. Also, its unique self-equalized doublesideband signaling renders the multi-band transceiver immune to inter-symbol

👥 作者与机构

Wei-Han Cho1, Yilei Li1, Yuan Du1, Chien-Heng Wong1,