A 4GS/s 13b Pipelined ADC with Capacitor and Amplifier Sharing in 16nm CMOS

📋 论文概要

该论文提出了一种在16nm CMOS工艺下实现的4GS/s 13位流水线ADC，通过电容和放大器共享技术显著降低了功耗和芯片面积，解决了高速高分辨率ADC设计中的能效瓶颈问题。

💡 主要创新点

• 采用电容共享技术，减少电容总数，从而降低面积和功耗。
• 采用放大器共享技术，减少有源放大器数量，进一步优化功耗。
• 在16nm先进工艺下实现4GS/s采样率与13位分辨率的高性能组合。

🏷 关键词

📄 原文摘要

Giuseppe Cusmai1, Sha-Ting Lin3, Cheng-Hsun Yang3, Gregory Unruh1, Sunny Raj Dommaraju1, Mo M. Zhang1, Po Tang Yang3, Wei-Ting Lin3, Xi Chen1, Dongsoo Koh1, Qingqi Dou1, H. Mohan Geddada1, Juo-Jung Hung1, Massimo Brandolini1, Young Shin1, Hung-Sen Huang3, Chun-Ying Chen1, Ardie Venes1 Broadcom, Irvine, CA, 2now with Tongji University, Shanghai, China, Broadcom, Hsinchu, Taiwan 1 3 In recent years, we have seen the emergence of multi-GS/s medium-to-highresolution ADCs. Presently, SAR ADCs dominate low-speed applications and time-interleaved SARs are becoming increasingly popular for high-speed ADCs [1,2]. However the SAR architecture faces two key problems in simultaneously achieving multi-GS/s sample rates and high resolution: (1) the fundamental tradeoff of comparator noise and speed is limiting the speed of single-channel SARs, and (2) highly time-interleaved ADCs introduce complex lane-to-lane mismatches

👥 作者与机构

Jiangfeng Wu1,2, Acer Chou1, Tianwei Li1, Rong Wu1, Tao Wang1,