A 320mW 32Gb/s 8b ADC-Based PAM-4 Analog Front-End with Programmable Gain Control and Analog Peaking in 28nm CMOS

📋 论文概要

本文提出了一款基于ADC的PAM-4模拟前端芯片，采用28nm CMOS工艺，集成了可编程增益控制和模拟峰值增强功能，实现了320mW功耗下32Gb/s的数据传输速率，解决了高速有线通信中信道损伤补偿和带宽效率问题。

💡 主要创新点

• 首次在PAM-4 ADC前端中集成可编程增益控制与模拟峰值增强，优化了信号动态范围和带宽。
• 采用8位ADC和DSP架构，在极低功耗（320mW）下实现32Gb/s高速率传输。
• 基于28nm CMOS工艺，通过电路设计实现了高能效的模拟前端，满足下一代有线通信需求。

🏷 关键词

📄 原文摘要

introduced in recent years for next generation wireline communication systems for more efficient use of the available link bandwidth. High-speed ADCs with digital signal processing (DSP) can provide robust performance for such systems to compensate for the severe channel impairment as the data rate continues to increase. ADC-based receivers with NRZ format for 10Gbps serial links have been developed [1-3]. For an ADC with a conversion rate of more than 16GS/s, the previous developments have the ADC input directly driving N-way interleaved structures [4-5]. Driving externally allows for higher input amplitude to relax the noise requirement of the ADC. However, the heavy load capacitance presented by the ADC results in degraded return loss and additional insertion loss in the system.

👥 作者与机构

Delong Cui1, Heng Zhang1, Nick Huang1,2, Ali Nazemi1, Burak Catli1,

Hyo Gyuem Rhew1, Bo Zhang1, Afshin Momtaz1, Jun Cao1 Broadcom, Irvine, CA, now with Apple, Cupertino, CA 1 2 Multilevel modulation formats, such as PAM-4, have been