Voltage-Scalable Frequency-Independent Quasi-Resonant Clocking Implementation of a 0.7-to-1.2V DVFS System

📋 论文概要

该论文提出了一种电压可缩放、频率无关的准谐振时钟（QRC）实现方案，解决了传统谐振时钟在宽电压-频率（VF）范围内可扩展性差的问题，从而支持0.7V至1.2V的动态电压频率调整（DVFS）系统。

💡 主要创新点

• 提出准谐振时钟（QRC）架构，实现频率无关的谐振操作，克服了传统谐振时钟对频率的依赖性。
• 通过电压可缩放设计，使QRC能在0.7V至1.2V的宽电压范围内高效工作，支持DVFS系统。
• 在测试芯片中验证了QRC的功耗优势，展示了其在宽工作范围内的时钟功耗降低能力。

🏷 关键词

📄 原文摘要

Clock power remains a substantial contributor to power dissipation, from ultralow-power to high-performance systems [1, 2, 3]. Recently, resonant clocking has been shown to achieve power reduction in clock distribution networks [2, 3]. However, the limited voltage-frequency (VF) scalability of resonant clocking implementations remains a key drawback. Continued aggressive use of DVFS will require efficient resonant clocking across the increasingly wider operating range of the system. In this paper, we present a test chip implementing quasi-resonant clocking (QRC), incorporating a voltage-scalable, frequency-independent and DVFS-enabled resonant clock architecture. The test chip achieves a 32-to-47% clock power reduction over a 0.7-to-1.2V supply-voltage range. Figure 19.6.1 illustrates existing resonant-clocking techniques and the QRC approach. Standard resonant-clocked systems employ an inductor to form an LC

👥 作者与机构

Fahim U. Rahman, Visvesh S. Sathe

University of Washington, Seattle, WA