A 4×4×2 Homogeneous Scalable 3D Network-on-Chip Circuit with 326MFlit/s 0.66pJ/b Robust and Fault-Tolerant Asynchronous 3D Links

📋 论文概要

本文提出了一种4×4×2同构可扩展3D片上网络电路，采用异步容错设计，实现了326MFlit/s的吞吐量和0.66pJ/b的能效，解决了3D集成中通信距离缩短带来的计算密度提升问题。

💡 主要创新点

• 提出了一种同构可扩展的3D NoC架构，支持垂直堆叠的2层4×4网格，实现高效的三维通信。
• 采用异步电路设计，增强了系统的鲁棒性和容错能力，同时降低了功耗。
• 实现了高吞吐量（326MFlit/s）和低能耗（0.66pJ/b），适用于4G基带处理等计算密集型应用。

🏷 关键词

📄 原文摘要

Christian Bernard1, Florian Darve1, Didier Lattard1, Ivan Miro-Panades1, Cristiano Santos1, Fabien Clermidy1, Severine Cheramy1, Frederic Petrot2, Eric Flamand3, Jean Michailos4 CEA-LETI-MINATEC, Grenoble, France, Tima Laboratory, Grenoble, France, 3 STMicroelectronics, Grenoble, France, 4 STMicroelectronics, Crolles, France 1 2 By shortening communication distance across dies, 3D technologies are a key to continued improvements in computing density. For 4G telecom baseband processing, specific computing units arranged in a regular network-on-chip (NoC) array provide power-efficient computation [1]. However, for advanced MIMO processing, more computing power is required when the number of antennas increases. This paper presents a homogeneous 3D circuit composed of regular tiles assembled using a 4×4×2 network-on-chip, using robust and fault tolerant asynchronous 3D links, providing 326MFlit/s @ 0.66pJ/b, fabricated in CMOS

👥 作者与机构

Pascal Vivet1, Yvain Thonnart1, Romain Lemaire1, Edith Beigne1,