A 2.4GHz 1.5mW Digital MDLL Using Pulse-Width Comparator and Double Injection Technique in 28nm CMOS

📋 论文概要

本文提出了一种基于脉冲宽度比较器和双注入技术的2.4GHz数字MDLL，在28nm CMOS工艺下实现了1.5mW的低功耗。该设计解决了传统MDLL倍频因子受限的问题，通过双注入技术有效抑制了抖动累积，实现了低抖动时钟生成。

💡 主要创新点

• 采用脉冲宽度比较器替代传统鉴相器，提高了相位检测精度并降低了功耗。
• 提出双注入技术，通过两次注入参考时钟边沿，显著增大了有效环路带宽，从而抑制振荡器相位噪声并支持更高的倍频因子。

🏷 关键词

📄 原文摘要

low-jitter clock generator, as it does not suffer much from jitter accumulation [1-4]. By periodically replacing the output edge of the oscillator by a clean edge of the reference, an MDLL has a large effective loop bandwidth for oscillator phase noise, which cannot be obtained in a PLL. With this advantage in mind, several MDLLs have been implemented recently [2], [3]. Unfortunately, these works are limited in their practical use as the frequency multiplication factor is only 4 [2] or 8 [3]. While the prior works show good jitter performance, it is primarily due to their wide effective loop bandwidth of nearly one hundred MHz that arises from using reference frequencies of 375 to 575MHz. It is much more challenging to achieve same level of jitter performance if the multiplication factor is increased and

👥 作者与机构

Hyunik Kim1,2, Yongjo Kim1, Taeik Kim2, Hojin Park2, SeongHwan Cho1

KAIST, Daejeon, Korea, Samsung Electronics, Hwaseong, Korea 1 2 A multiplying delay-locked loop (MDLL) is an attractive architecture for a