A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an

📋 论文概要

该论文实现了一款采用20nm CMOS工艺的8Gb GDDR5 DRAM，数据速率达到9Gb/s/pin，为当时最高速率的GDDR5 DRAM。为了解决高速运行下的可靠性问题，论文引入了NBTI监测器、均衡和占空比校正的WCK时钟接收器以及CML-to-CMOS转换器等电路技术。

💡 主要创新点

• 集成NBTI监测器，实时监控负偏置温度不稳定性，提升长期可靠性。
• 采用具有均衡和占空比校正模式的WCK时钟接收器，改善高速时钟信号质量。
• 设计CML-to-CMOS转换器，优化高速信号转换效率。

🏷 关键词

📄 原文摘要

Hye-Yoon Joo, Seung-Jun Bae, Young-Soo Sohn, Young-Sik Kim, Kyung-Soo Ha, Min-Su Ahn, Young-Ju Kim, Yong-Jun Kim, Young-Ju Kim, Ju-Hwan Kim, Won-Jun Choi, Chang-Ho Shin, Soo Hwan Kim, Byeong-Cheol Kim, Seung-Bum Ko, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin Samsung Electronics, Hwaseong, Korea A 9Gb/s/pin 8Gb GDDR5 DRAM is implemented using a 20nm CMOS process. To cover operation up to 9Gb/s, which is the highest data-rate among implemented GDDR5 DRAMs [1], this work includes an NBTI monitor, a WCK clock receiver with equalizing and duty-cycle correction modes, CML-to-CMOS converters with wide range operation, active resonant loads at the end of WCK lane, and an on-chip de-emphasis circuit at a 4-to-1 multiplexer output as shown in Fig. 18.1.1. In addition, extra power pads improve the power distribution and release the frequency limitation at the memory core. As CMOS technology scales down, negative-bias temperature instability (NBTI)

👥 作者与机构

NBTI Monitor, Jitter Reduction Techniques and, Improved Power Distribution