A 3.2GHz Digital Phase-Locked Loop with Background Supply-Noise Cancellation

📋 论文概要

该论文提出了一种3.2GHz数字锁相环（PLL），通过背景电源噪声消除技术来抑制电源噪声对PLL抖动性能的影响，避免了传统去耦电容或低压差稳压器（LDO）带来的面积和功耗开销。

💡 主要创新点

• 提出背景电源噪声消除技术，实时校准环内噪声影响，无需额外模拟滤波或稳压器。
• 全数字实现，易于集成到先进CMOS工艺中，降低面积和成本。
• 通过数字域的后台处理，在不中断PLL正常工作的条件下持续抑制电源噪声。

🏷 关键词

📄 原文摘要

Phase-locked loops (PLLs) are widely used in various applications such as processors, consumer electronics, and wireline communication systems. When digital circuits and a PLL with a ring oscillator are integrated together, the power supply noise may degrade the jitter performance of the PLL. To lower the supplynoise sensitivity of a PLL, several approaches [1-5] have been proposed. A passive decoupling capacitor and/or a low-dropout (LDO) regulator [1] can be used to suppress the supply noise. However, the decoupling capacitor occupies large area and the LDO requires additional power and area. In [2], a calibration mechanism is used to close and open the loop on an alternating basis, increasing the settling time. In [3], an extra foreground frequency calibration is needed to ensure the PLL is at the correct sub-band and supply voltage – it may be susceptible to process, voltage and temperature (PVT) variations. The approach in [4] requires

👥 作者与机构

Che-Wei Yeh, Cheng-En Hsieh, Shen-Iuan Liu

National Taiwan University, Taipei, Taiwan