A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V Shared Logarithmic Floating Point Unit for Acceleration of Nonlinear Function Kernels in a Tightly Coupled Processor Cluster

📋 论文概要

该论文提出了一种在65nm CMOS工艺下实现的共享对数浮点单元（LNS-FPU），用于加速非线性函数核的计算。通过采用对数数制（LNS）替代传统浮点运算，简化了乘法、除法和指数等复杂操作，从而在0.8V电压下实现了每FLOP仅6.4至29.2pJ的高能效，适用于物联网和可穿戴设备等需要大动态范围的应用。

💡 主要创新点

• 提出基于对数数制（LNS）的共享浮点单元架构，将复杂的浮点乘法、除法、指数运算转换为简单的加法、减法和查找表操作，显著降低功耗和面积。
• 采用共享设计，使多个处理单元可复用该LNS-FPU，进一步减少硬件开销，在65nm CMOS工艺下实现0.8V超低电压工作，能效达到6.4-29.2pJ/FLOP。
• 针对SLAM、立体视觉等非线性函数核进行优化，在保持足够动态范围的同时，相比传统单精度浮点单元能效提升数倍。

🏷 关键词

📄 原文摘要

many application areas, such as IoT and wearables. While for some applications, integer and fixed-point processor instructions suffice, others (e.g. simultaneous localization and mapping – SLAM, stereo vision, nonlinear regression and classification) require a larger dynamic range, typically obtained using single/double-precision floating point (FP) instructions. Logarithmic number systems (LNS) have been proposed [1,2] as an energy-efficient alternative to conventional FP, as several complex operations such as MUL, DIV, and EXP translate into simpler arithmetic operations in the logarithmic space and can be efficiently calculated using integer arithmetic units. However, ADD and SUB become nonlinear and have to be approximated by look-up tables (LUTs) and

👥 作者与机构

Michael Gautschi1, Michael Schaffner1, Frank K. Gürkaynak1,

Luca Benini1,2 ETH Zurich, Zurich, Switzerland, 2University of Bologna, Bologna, Italy 1 Energy-efficient computing and ultra-low-power operation are requirements for