A Pin-Efficient 20.83Gb/s/wire 0.94pJ/bit Forwarded Clock CNRZ-5-Coded SerDes up to 12mm for MCM Packages in 28nm CMOS

📋 论文概要

本文提出了一种用于多芯片模块（MCM）封装的引脚高效前向时钟CNRZ-5编码串行器/解串器（SerDes），在28nm CMOS工艺中实现了每线20.83Gb/s的数据速率和0.94pJ/bit的能效，支持长达12mm的传输距离。该设计解决了高密度存储器接口和大芯片分割等应用中高速信号在封装基板上传输的挑战。

💡 主要创新点

• 采用CNRZ-5编码技术，提高引脚效率，在相同引脚数下实现更高数据吞吐量。
• 前向时钟架构简化了接收端的时钟恢复，降低了功耗和复杂度。
• 针对MCM封装优化了信号完整性，支持12mm片内互连，同时保持低能耗。

🏷 关键词

📄 原文摘要

Brian Holden1, Ali Hormati1, Peter Hunt2, Margaret Johnston1, John Keay2, Sergio Pesenti1, Richard Simpson2, David Stauffer1, Andrew Stewart2, Giuseppe Surace2, Armin Tajalli1, Omid Talebi Amiri1, Anton Tschank2, Roger Ulrich1, Christoph Walter1, Fabio Licciardello1, Yohann Mogentale1, Anant Singh1 Kandou Bus, Lausanne, Switzerland, Kandou Bus, Northampton, United Kingdom 1 2 High-speed signaling over package substrates is key to delivering the promise of 2.5D integration. Applications abound and include high-density memory interfaces, sub-division of large dies to increase yield and lower development time, sub-division of a die to achieve upward or downward scalability, or connecting to an off-chip SerDes or optics engine. Each of these in-package applications typically has high throughput and onerously low power constraints along with a low-loss channel. Several solutions have been proposed. Interposer

👥 作者与机构

Amin Shokrollahi1, Dario Carnelli1, John Fox2, Klaas Hofstra1,