A 1.2e- Temporal Noise 3D-Stacked CMOS Image Sensor with Comparator-Based Multiple-Sampling PGA

📋 论文概要

该论文提出了一种用于移动应用的3D堆叠CMOS图像传感器，通过采用比较器基多采样PGA和2阶增量ΔΣ ADC，实现了1.2e-的极低时域噪声和高效能。主要解决了传统图像传感器在面积和噪声之间的权衡问题。

💡 主要创新点

• 采用3D堆叠结构将像素和电路分离，底片使用65nm CMOS工艺以集成更多功能，有效减小芯片面积。
• 提出基于比较器的多采样PGA技术，结合2阶增量ΔΣ ADC，以低功耗实现指数级采样，显著降低时域噪声至1.2e-。

🏷 关键词

📄 原文摘要

2e-, 3D-stacked CMOS image sensor (CIS) for mobile applications. A key motivation for using a stacked configuration is to minimize the chip area. Also, since numerous components must be integrated into the bottom chip, a scaled 65nm CMOS process is adopted for the bottom chip. The developed CIS features 1.2e- temporal noise with extremely high power efficiency by employing a multiple-sampling (MS) technique. A 2nd-order incremental ΔΣ ADC with inverter-based switched-capacitor integrator realizes the MS technique with low power [1]. However, an exponential number of samples are required to reduce the quantization noise, and conversion speed worsens with higher bit resolution. An extended counting ADC, which is a blend of folding integration and

👥 作者与机构

Kei Shiraishi, Yasuhiro Shinozuka, Tomonori Yamashita,

Kazuhide Sugiura, Naoto Watanabe, Ryuta Okamoto, Tatsuji Ashitani, Masanori Furuta, Tetsuro Itakura Toshiba, Kawasaki, Japan This paper presents a 1