A Reconfigurable Dual-Port Memory with Error Detection and Correction in 28nm FDSOI

📋 论文概要

该论文提出了一种在28nm FDSOI工艺中实现的可重构双端口存储器，集成了错误检测与纠正（EDAC）功能，旨在解决低电压下SRAM因PVT变化导致的传感延迟变化和性能裕度问题。通过可重构架构和EDAC，该设计降低了低电压操作所需的保护带，提升了电压可扩展性。

💡 主要创新点

• 提出可重构双端口SRAM架构，支持灵活配置以满足不同应用需求。
• 集成错误检测与纠正电路，在低电压下有效补偿PVT变化引起的传感延迟变化，减少性能裕度。
• 在28nm FDSOI工艺中实现，展示了低电压下可靠工作的能力。

🏷 关键词

📄 原文摘要

systems-on-chip and usually limits their voltage scalability, due to the major impact of process/voltage/temperature (PVT) variations at low voltages [1]. Assist techniques to extend SRAM operating voltage range improve the bit cell read/write stability [1-5], but cannot mitigate variations in the internal sensing delay that is needed to develop the targeted bitline (BL) voltage. Hence, large guard bands and performance margins are still needed to ensure correct operation. These margins increase as supply voltage is lowered (Fig. 17.3.1) and must be addressed especially when the SRAM is coupled with margin-less processor designs (e.g., Razor). This paper introduces a Razor-style [6] error detection and correction (EDAC)

👥 作者与机构

Mahmood Khayatzadeh1, Mehdi Saligane1, Jingcheng Wang1,

Massimo Alioto2, David Blaauw1, Dennis Sylvester1 University of Michigan, Ann Arbor, MI, National University of Singapore, Singapore, Singapore 1 2 SRAM is a key building block in