A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V Supply in 28nm CMOS FDSOI

📋 论文概要

本文提出一种在28nm CMOS FDSOI工艺下，采用1V电源实现1.3Vppd输出摆幅的45Gb/s PAM-4发射器，解决了高速串行接口在低电压下需要高输出摆幅的关键问题，支持400Gb/s以太网标准的演进需求。

💡 主要创新点

• 利用28nm FDSOI工艺的体偏置技术，在1V低电源电压下实现1.3Vppd的大输出摆幅，突破传统电压摆幅限制。
• 设计高效的PAM-4编码与驱动器架构，在45Gb/s速率下保持信号完整性，并采用前向误差校正（FEC）兼容设计。

🏷 关键词

📄 原文摘要

electrical link technology to support 400Gb/s standards is underway [1-5]. Physical constraints paired to the small area available to dissipate heat, impose limits to the maximum number of serial interfaces and therefore their minimum speed. As such, aggregation of currently available 25Gb/s systems is not an option, and the migration path requires serial interfaces to operate at increased rates. According to CEI-56G and IEEE P802.3bs emerging standards, PAM-4 signaling paired to forward error correction (FEC) schemes is enabling several interconnect applications and low-loss profiles [1]. Since the amplitude of each eye is reduced by a factor of 3, while noise power is only halved, a high transmitter (TX) output amplitude is key to preserve high SNR.

👥 作者与机构

Matteo Bassi1, Francesco Radice2, Melchiorre Bruccoleri2,

Simone Erba3, Andrea Mazzanti1 University of Pavia, Pavia, Italy, 2STMicroelectronics, Cornaredo, Italy, STMicroelectronics, Pavia, Italy 1 3 The development of next-generation