A 6.5-to-23.3fJ/b/mm Balanced ChargeRecycling Bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with Clock Forwarding and Low-Crosstalk Contraflow Wiring

📋 论文概要

该论文提出了一种平衡电荷回收总线（BCRB），通过堆叠两个CMOS重复线链路实现二次方功耗节省，解决了大芯片中全局互连功耗日益增长的问题。在16nm FinFET CMOS工艺下，该总线实现了1.7至2.6 Gb/s/线的数据传输速率，每比特每毫米能耗仅为6.5至23.3 fJ。

💡 主要创新点

• 提出平衡电荷回收总线（BCRB）架构，通过堆叠两个CMOS重复线链路实现二次方功耗节省。
• 采用时钟转发技术，支持高速数据传输并降低功耗。

🏷 关键词

📄 原文摘要

Stephen G. Tell1, Thomas H. Greer III1, C. Thomas Gray1, William J. Dally2 Nvidia, Durham, NC, 2Nvidia, Santa Clara, CA 1 Signaling over chip-scale global interconnect is consuming a larger fraction of total power in large processor chips, as processes continue to shrink. Solving this growing crisis requires simple, low-energy and area-efficient signaling for high-bandwidth data buses. This paper describes a balanced charge-recycling bus (BCRB) that achieves quadratic power savings, relative to signaling with fullswing CMOS repeaters. The scheme stacks two CMOS repeated wire links, one operating in the Vtop domain, between Vdd and Vmid=Vdd/2, the other, Vbot, between Vmid and GND. Unlike previous work [1], we require no voltage regulator to maintain the Vmid voltage at Vdd/2, to compensate for differences in data activity in Vtop and Vbot domains. The BCRB also uses simple single-ended signaling, to achieve higher bandwidth per unit bus width than differential buses

👥 作者与机构

John M. Wilson1, Matthew R. Fojtik1, John W. Poulton1, Xi Chen2,