A 1.2V 64Gb 8-Channel 256GB/s HBM DRAM with Peripheral-Base-Die Architecture and Small-Swing Technique on Heavy Load Interface

📋 论文概要

本文提出了一款1.2V 64Gb 8通道256GB/s的HBM DRAM，采用外围基底芯片架构和小摆幅技术以应对重负载接口，解决了高性能计算和服务器市场中对高带宽和灵活容量配置的需求。

💡 主要创新点

• 采用外围基底芯片架构，将外围电路集成在基底芯片上，提高了设计灵活性和信号完整性。
• 提出小摆幅技术，在重负载接口上降低功耗并提升数据传输速率。
• 支持4、8甚至2层配置，满足不同客户对容量和带宽的需求。

🏷 关键词

📄 原文摘要

Dae Suk Kim, Chunseok Jeong, Tae Sik Yun, Hongjung Kim, Ho Sung Cho, Yeon Ok Kim, Jae Hwan Kim, Jin Ho Kim, Sangmuk Oh, Hyun Sung Lee, Ki Hun Kwon, Dong Beom Lee, Young Jae Choi, Jeajin Lee, Hyeon Gon Kim, Jun Hyun Chun, Jonghoon Oh, Seok Hee Lee SK hynix, Icheon, Korea Because of the expansion of high performance computing (HPC) and server market, demand for HBM DRAM is increasing. With this market flow, diverse customers require various HBM product families. One customer requirement is full bandwidth with less density. Therefore, this work presents a HBM DRAM, which supports 4, 8, and even 2-hi stacks with full-bandwidth performance. The HBM DRAM adopts a peripheral base die architecture, which has smaller chip size and good testability resulting in more manufacturability. This architecture can compensate for process variation, since this problem among core dies within the same known good stacked die (KGSD) is the key issue of TSV-based stacked

👥 作者与机构

Jong Chern Lee, Jihwan Kim, Kyung Whan Kim, Young Jun Ku,