A 25Gb/s ADC-Based Serial Line Receiver in 32nm CMOS SOI

📋 论文概要

该论文设计了一个25Gb/s的基于ADC的串行线接收器，采用32nm CMOS SOI工艺，旨在解决高速串行通信中模拟电路对工艺、电压、温度（PVT）敏感的问题。通过数字基带处理替代传统模拟均衡，实现了PVT无关的高性能接收。

💡 主要创新点

• 采用ADC-based架构实现25Gb/s高速串行接收，利用数字信号处理替代模拟均衡，提升PVT鲁棒性。
• 在32nm CMOS SOI工艺中集成高速ADC和数字均衡器，实现低功耗、小面积的高性能接收。
• 通过数字域自适应均衡和时钟恢复，支持25Gb/s数据率下的可靠链路通信。

🏷 关键词

📄 原文摘要

Thomas Toifl2, Yong Liu3, Ankur Agrawal1, Peter Buchmann2, Alexander Rylyakov4, Michael Beakes1, Benjamin Parker1, Mounir Meghelli1 IBM T. J. Watson Reseach Center, Yorktown Heights, NY, IBM Zurich Research Laboratory, Rüschlikon, Switzerland, 3 now with Shanghai Jiao Tong University, Shanghai, China, 4 now with Coriant Advanced Technology Group, New York, NY 1 2 As CMOS devices continue to scale down in voltage and area, digital-based highspeed serial I/Os [1] become increasingly competitive with analog-based designs [2,3]. In addition to offering the PVT-independent performance of digital functions and superior power and area scaling to future technology nodes, digital-based I/Os can support advanced line modulation techniques that will become necessary as long-reach electrical channel data rates scale to 56Gb/s and beyond. The key enablers of a digital receiver are power and area efficient analog to digital

👥 作者与机构

Sergey Rylov1, Troy Beukema1, Zeynep Toprak-Deniz1,