4Mb STT-MRAM-Based Cache with MemoryAccess-Aware Power Optimization and WriteVerify-Write / Read-Modify-Write Scheme

📋 论文概要

本文提出了一款4Mb的STT-MRAM缓存，通过内存访问感知的功耗优化技术以及写验证写/读修改写方案，解决了传统易失性存储器在填补CPU缓存与主存、主存与存储之间的性能差距时功耗过大的问题。

💡 主要创新点

• 提出了内存访问感知的功耗优化技术，根据不同的访问模式动态调整缓存功耗，降低整体能耗。
• 引入了写验证写（Write-Verify-Write）和读修改写（Read-Modify-Write）方案，在提高写入可靠性的同时进一步减少功耗。

🏷 关键词

📄 原文摘要

Keiichi Kushida1, Atsushi Kawasumi1, Hiroyuki Hara1, Keiko Abe1, Naoharu Shimomura1, Junichi Ito1, Shinobu Fujita1, Takashi Nakada2, Hiroshi Nakamura2 Toshiba, Kawasaki, Japan, University of Tokyo, Tokyo, Japan 1 2 Two performance gaps in the memory hierarchy, between CPU cache and main memory, and main memory and mass storage, will become increasingly severe bottlenecks for computing-system performance. Although it is necessary to increase memory capacity to fill these gaps, power also increases when conventional volatile memories are used. A new nonvolatile memory for this purpose has been anticipated. Storage class memory is used to fill the second gap. Many candidates exist: ReRAM, PRAM, and 3D-cross point type with resistive change RAM. However, nonvolatile last level cache (LLC) is used to fill the first gap. Advanced STT-MRAM has achieved sub-4ns read and write accesses with perpendicular magnetic tunnel junctions (p-MTJ) [1-2]. Furthermore, mature

👥 作者与机构

Hiroki Noguchi1, Kazutaka Ikegami1, Satoshi Takaya1, Eishi Arima2,