Post-Silicon Voltage-Guard-Band Reduction in a 22nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating

📋 论文概要

本文提出了一种在22nm图形执行核心中通过自适应电压缩放和动态功率管理来减少后硅电压保护带的方法。通过集成混合数字LDO/SCVR稳压器和保留触发器，实现了自主DVFS，降低了固有VMIN和泄漏功耗，从而在保证性能的同时缩小了电压裕量。

💡 主要创新点

• 采用自适应电压缩放技术，根据实际硅片特性动态调整电压，减少传统保守电压保护带带来的功耗浪费。
• 集成混合数字LDO/SCVR稳压器，在共享电源轨场景下实现低成本自主DVFS，支持多种电源模式切换。
• 利用保留触发器在停滞期间降低泄漏功耗，进一步优化整体能效。

🏷 关键词

📄 原文摘要

circuits to lower intrinsic VMIN, retention flops to reduce leakage power during stall periods, and a fully integrated hybrid digital LDO/SCVR regulator to provide a cost-effective means to realize autonomous DVFS under a shared-rail scenario [1-2]. In a conventional design, a conservative voltage guard band (VGB) is added to the nominal supply of each die to guarantee its correct operation at target frequency in the presence of worst-case delay degradation induced by inverse-temperature dependency (ITD) [3], device aging, and voltage droop. This VGB is determined from post-silicon characterization as the voltage shift needed by the worst-case die, assuming extreme aging usage conditions, while running a power virus load. In this paper, we present a graphics execution core that uses an in-situ tunable

👥 作者与机构

Minki Cho, Stephen Kim, Carlos Tokunaga, Charles Augustine,

Jaydeep Kulkarni, Krishnan Ravichandran, James Tschanz, Muhammad Khellah, Vivek De Intel, Hillsboro, OR A graphics execution core in 22nm combines SRAM array-assist