A 4.2μs-Settling-Time 3rd-Order 2.1GHz PhaseNoise-Rejection PLL Using a Cascaded TimeAmplified Clock-Skew Sub-Sampling DLL

📋 论文概要

该论文提出了一种采用级联时间放大时钟偏移子采样技术的3阶2.1GHz锁相环（PLL），通过3阶反馈环路实现大低频环路增益以抑制相位噪声，同时利用级联时间放大技术解决了高阶环路导致的建立时间恶化问题，实现了4.2μs的快速建立时间。

💡 主要创新点

• 提出了级联时间放大时钟偏移子采样技术，在子采样PLL中实现快速建立时间，克服传统子采样PLL建立时间慢的缺点。
• 采用3阶Type-III PLL架构，提供大低频环路增益，有效抑制VCO相位噪声和电源敏感性。
• 通过时间放大技术放大时钟偏移，提高子采样鉴相器的灵敏度，从而改善噪声性能。

🏷 关键词

📄 原文摘要

tuning range compared with LC-VCO-based PLLs. However, they typically have higher jitter and larger frequency drift due to high sensitivity to PVT variations. Several PLL architectures were proposed to reject the phase noise and reduce the frequency drift [1,2]. However, due to an architecture-level limitation, these phase-noise-rejection PLLs inevitably degrade the settling time. To suppress large phase noise (PN) and supply sensitivity, a Type-III PLL was proposed to provide a large low-frequency loop gain by using a 3rd-order feedback loop [1]. However, high-order feedback loop degrades stability and requires lowfrequency compensation zero, which needs a large loop filter and reduces the PN suppression bandwidth. To suppress the phase noise over a wide frequency

👥 作者与机构

Zhiqiang Huang1, Bingwei Jiang1, Lianming Li2, Howard Cam Luong1

Hong Kong University of Science and Technology, Hong Kong, China, Southeast University, Nanjing, China 1 2 Ring-VCO-based PLLs are popular because of their compact chip area and wide