Area-Efficient 1GS/s 6b SAR ADC with ChargeInjection-Cell-Based DAC

📋 论文概要

提出一种基于电荷注入单元DAC的6位1GS/s SAR ADC，通过新型DAC结构大幅减小芯片面积，解决了交织SAR ADC面积大导致伪影的问题，实现了单通道高速低面积转换。

💡 主要创新点

• 采用电荷注入单元代替传统电容DAC，显著减小DAC面积。
• 实现单通道1GS/s 6位SAR ADC，避免多位每周期架构的复杂性和额外面积开销。

🏷 关键词

📄 原文摘要

To support growing data bandwidths, high-speed moderate-resolution ADCs have become vital for high-speed serial links. Interleaved SAR ADCs achieve high sampling speeds and good energy efficiency. However a challenge is that these ADCs are large and therefore suffer from interleaving artifacts related to size [1]. Compact, efficient SAR ADCs are needed to address this problem. As an alternative, multiple-bit-per-cycle SAR ADCs deliver high speed from a single SAR ADC, but at the cost of significant added complexity (i.e., extra quantizers and capacitor DACs) and die area [2,3]. This work addresses the need for a fast, compact SAR ADC, with a 1GS/s SAR ADC that has the best Walden FOM and the smallest area among 5-to-6.3b ADCs published in ISSCC (see Fig. 27.3.1). We introduce a charge-injection SAR (or ciSAR), which is based on a chargeinjection DAC structure. The ADC achieves GHz sampling speed from a single

👥 作者与机构

Kyojin D. Choo, John Bell, Michael P Flynn

University of Michigan, Ann Arbor, MI