A 2.5GHz 7.7TOPS/W Switched-Capacitor Matrix Multiplier with Co-designed Local Memory in 40nm

📋 论文概要

该论文提出了一种无源开关电容矩阵乘法器（SCMM），通过协同设计的无位线存储器实现高能效矩阵乘法，在40nm工艺下达到2.5GHz工作频率和7.7TOPS/W的能效。

💡 主要创新点

• 采用300aF单位边缘电容实现高速低能耗的电荷域计算
• 协同设计无位线存储器，消除传统位线功耗瓶颈

🏷 关键词

📄 原文摘要

Matrix multiplication, enabled by multiply-and-accumulate hardware, is ubiquitous in signal processing, computer graphics, machine learning, and optimization. Many important applications with inherent robustness to reduced precision for matrix multiplication, e.g. inference for neural networks [1], can take advantage of analog signal processing for energy efficiency. This work presents a 64-cycle programmable passive Switched-Capacitor Matrix Multiplier (SCMM) with codesigned bitline-less memory. The design exploits 300aF unit fringe capacitors for high speed and low energy charge-domain processing and contains the input DAC, multiply-and-accumulate SAR ADC, and local memory. Two applications of the SCMM are demonstrated: 1) an analog front-end for an image classifier system, which reduces A/D conversions by 21x and multiply-and-accumulate compute energy by 11x over a conventional system, and 2) a co-processing

👥 作者与机构

Edward H. Lee, S. Simon Wong

Stanford University, Stanford, CA