A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS

📋 论文概要

该论文提出了一款采用28nm CMOS工艺的连续时间1-2级联MASH ADC，实现了465MHz信号带宽和69dB动态范围，总功耗为930mW，解决了宽带通信系统中高带宽与高动态范围之间的折衷问题。

💡 主要创新点

• 采用连续时间MASH架构，通过1-2级级联实现宽带高动态范围。
• 在465MHz带宽内达到69dB DR和65dB峰值SNDR，同时保持930mW的低功耗。

🏷 关键词

📄 原文摘要

Cambridge, MA 1 2 The width of RF bands commonly used for cellular telecommunications has grown from 35-to-75MHz for 2G/3G/4G platforms to 100-to-200MHz for today’s LTE, and the desire for relaxed image-rejection filtering has pushed the direct IF sampling frequencies to 300+ MHz. This paper presents a continuous-time (CT) multi-stage noise-shaping (MASH) ADC IC that achieves 69dB of DR over a 465MHz signal bandwidth with a combined power consumption of 930mW from ±1.0V/1.8V supplies. The ADC IC is implemented in 28nm CMOS and achieves a peak SNDR of 65dB, a small-signal noise-spectral density (NSD) of −156dBFS/Hz, and a figure-of-merit (FOM) of 156dB over a signal bandwidth of 465MHz. Figure 15.5.1 shows the system-level schematic of the CT 1-2 MASH ADC. With

👥 作者与机构

Yunzhi Dong1, Jialin Zhao1, Wenhua Yang1, Trevor Caldwell2,

Hajime Shibata2, Richard Schreier2, Qingdong Meng3, Jose Silva1, Donald Paterson1, Jeffrey Gealow1 Analog Devices, Wilmington, MA, Analog Devices, Toronto, ON, Canada, 3 Analog Devices,