A Scalable 28GHz Coupled-PLL in 65nm CMOS with Single-Wire Synchronization for LargeScale 5G mm-Wave Arrays

📋 论文概要

本文提出了一种可扩展的28GHz耦合锁相环（PLL），采用65nm CMOS工艺，通过单线同步技术实现大规模5G毫米波阵列中不同单元之间的相位一致性。解决了瓦片式MIMO/相控阵中LO分布和相位噪声的挑战。

💡 主要创新点

• 提出可扩展的28GHz耦合PLL架构，支持大规模毫米波阵列的瓦片式集成。
• 采用单线同步技术，实现不同单元IC/PCB之间的相位相干性，简化了LO分布。

🏷 关键词

📄 原文摘要

Demonstrations of mm-Wave arrays with >50 elements in silicon has led to an interest in large-scale mm-Wave MIMO arrays for 5G networks, which promise substantial improvements in network capacity [1,2]. Practical considerations result in such arrays being developed with a tiled approach, where N unit cells with M elements each are tiled to achieve large MIMO/phased arrays with NM elements [2]. Achieving stringent phase-noise specifications and scalable LO distribution to maintain phase coherence across different unit cell ICs/PCBs are a critical challenge. In this paper, we demonstrate a scalable, single-wiresynchronization architecture and circuits for mm-Wave arrays that preserve the simplicity of daisy-chained LO distribution, compensate for phase offset due to interconnects, and provide phase-noise improvement with increasing number of PLLs [3]. Measurements on a scalable 28GHz prototype demonstrate a 21%

👥 作者与机构

Abhishek Agrawal, Arun Natarajan

Oregon State University, Corvallis, OR