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ISSCC 2016Session 23 · ELECTRICAL AND OPTICAL LINK INNOVATIONSWireline I/O65nm/0.18µm CMOS

A 6Gb/s 3-Tap FFE Transmitter and 5-Tap DFE Receiver in 65nm/0.18µm CMOS for NextGeneration 8K Displays

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📋 论文概要

该论文针对下一代8K电视显示面板接口的数据速率超过140Gb/s的需求,设计了一款6Gb/s的3抽头前馈均衡(FFE)发射机和5抽头判决反馈均衡(DFE)接收机,采用65nm/0.18µm CMOS工艺,解决了大屏幕高通道损耗下的高速均衡问题。

💡 主要创新点

工艺节点
65nm/0.18µm CMOS
重要性
发表年份
ISSCC 2016

🏷 关键词

FFEDFE8K显示CMOS均衡器

📄 原文摘要

Sabarish Sankaranarayanan, Chaofeng Huang, Minghui Han, Gaurav Malhotra, Jalil Kamali, Amir Amirkhany, Wei Xiong Samsung Semiconductor, San Jose, CA The continuous increase in the resolution, color depth and refresh rate of TVs has driven the video data rate of the display panel interface from the timing controller to the pixel drivers in a typical 4K (UHD) TV to 36Gb/s. For the next generation 8K (Quad-UHD) TV, this number is expected to exceed 140Gb/s. The everincreasing screen sizes pose an additional challenge by introducing high channel losses in the data lanes, requiring advanced equalization techniques such as decision feedback equalization (DFE) in the receiver, which hitherto has not been used in a display panel interface. At the same time, the requirement to integrate the receiver into the high-voltage pixel driver IC limits the technology of choice to 0.18μm CMOS. To achieve the required high-speed performance while

👥 作者与机构

Mohammad Hekmat, Sanquan Song, Nancy Jaffari,

分类:Wireline I/O · 年份:ISSCC 2016