A 12b 2GS/s Dual-Rate Hybrid DAC with Pulsed Timing-Error Pre-Distortion and In-Band Noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS

📋 论文概要

提出一种12位2GS/s的双速率混合DAC架构，通过LSB路径过采样和MSB路径奈奎斯特降低电流单元数量，并采用脉冲时序误差预失真和带内噪声消除技术提升线性度，实现了超过74dBc的无杂散动态范围。

💡 主要创新点

• 提出双速率混合DAC架构，结合过采样LSB路径和奈奎斯特MSB路径，减少电流单元数量并降低匹配要求。
• 采用脉冲时序误差预失真技术，补偿高速切换中的时序失配。
• 引入带内噪声消除机制，改善带内噪声性能，进一步提升线性度。

🏷 关键词

📄 原文摘要

A dual-rate hybrid DAC is proposed in [1] that shows a path toward high speed/linearity in scaled technology. In this hybrid architecture, the resolution of the DAC is achieved through an oversampled LSB path, while its output power is mostly delivered by a Nyquist MSB path, resulting in a reduced number of currentsteering cells and relaxed amplitude-matching requirement via digital pre-distortion in the LSB path. To further extend the DAC bandwidth, this architecture incurs high cost, such as higher oversampling ratio in the LSB path and an increasing number of MSB bits. Both cases can increase the complexity of the analog circuit. Moreover, when the DAC output frequency is higher, timing error effects (including delay and duty-cycle errors) become more important than that of the amplitude error. In this work, we propose: a) an in-band noisecancellation scheme that extends the overall bandwidth with less overhead, and

👥 作者与机构

Shiyu Su, Mike Shuo-Wei Chen

University of Southern California, Los Angeles, CA