A 1.5V 33Mpixel 3D-Stacked CMOS Image Sensor with Negative Substrate Bias

📋 论文概要

该论文提出了一种1.5V、33兆像素的3D堆叠CMOS图像传感器，采用负衬底偏压技术以提高像素性能，并解决3D堆叠中像素阵列与外围电路分离的面积效率问题。

💡 主要创新点

• 采用负衬底偏压技术，降低暗电流并改善像素性能。
• 3D堆叠架构实现像素阵列与外围电路分离，支持计算成像模块集成，追求100%阵列与芯片面积比。

🏷 关键词

📄 原文摘要

image sensors. In addition, 3D stacking separates pixel array and peripheral circuits. As such, computational imaging blocks (stereo vision, array camera, reconfigurable instruction cell array, etc.) can integrate with sensor circuits while leveraging advanced CMOS technologies including FinFET. To accommodate this trend, we need to design blocks such as comparators, readouts, transmitters, and PLLs, using digital architectures in logic processes with a minimum number of resistors and capacitors. Achieving 100% array-to-chip area ratio is an ultimate goal of 3D CIS. For this reason, all peripheral circuits must be under the pixel array. However, row and column circuits may overlap at the corner if both pitches are equal to pixel pitch. To avoid this issue, we make row and pixel pitch the same, and shrink column

👥 作者与机构

Charles Chih-Min Liu, Manoj M. Mhala, Chin-Hao Chang,

Honyih Tu, Po-Sheng Chou, Calvin Chao, Fu-Lung Hsueh TSMC, Hsinchu, Taiwan 3D stacking and computational imaging are two major driving forces for CMOS