A 280µW 24kHz-BW 98.5dB-SNDR Chopped Single-Bit CT ΔΣM Achieving <10Hz 1/f Noise Corner Without Chopping Artifacts

📋 论文概要

该论文提出了一种280µW功耗、24kHz带宽、98.5dB SNDR的斩波单比特连续时间ΔΣ调制器，实现了低于10Hz的1/f噪声转角且无斩波伪影。解决了传统CTDSM中因闪烁噪声导致的低频精度下降以及斩波技术引入伪影的问题。

💡 主要创新点

• 采用斩波技术有效抑制1/f噪声，同时通过电路设计避免斩波伪影，实现极低噪声转角。
• 在单比特CT ΔΣM中实现98.5dB SNDR的高精度，功耗仅280µW，适用于工业低频高精度应用。

🏷 关键词

📄 原文摘要

IIT Madras, Chennai, India Many industrial applications require high-resolution ADCs whose low-frequency performance is important. CTDSMs are attractive due to their implicit antialiasing and resistive inputs. However, their low-frequency precision is degraded by flicker noise. The loop filter of such modulators is usually realized using active-RC techniques, and the CTDSMs’ 1/f noise is mostly due to the input stage of the 1st OTA. Using large input devices to reduce 1/f noise greatly increases area occupied by the input stage, and degrades linearity due to the increased parasitic capacitance at the OTA virtual ground. Another way of addressing 1/f noise is to chop the OTA, to modulate its flicker noise out of the signal band. This, however, degrades the CTDSM’s SQNR by aliasing shaped quantization noise in-band. This is particularly problematic with 1b ΔΣ ADCs, whose out-of-band noise spectral density is very high. The

👥 作者与机构

Sujith Billa, Amrith Sukumaran, Shanthi Pavan