⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种在28nm CMOS工艺下实现的12Gb/s、0.9mW/Gb/s宽带宽注入型时钟数据恢复(CDR)电路，通过数字频率控制算法实现了无参考频率的频率捕获，解决了传统CDR需要外部参考时钟的问题。
Jacob Wysocki2, Koki Uchino1, Yoshifumi Miyajima3, Yosuke Ueno1, Kenichi Maruko1, Zhiwei Zhou1, Hideyuki Matsumoto1, Hideyuki Suzuki1, Norio Shoji1 Sony, Tokyo, Japan, Mixed Signal Systems, Scotts Valley, CA, 3 Sony LSI Design, Kanagawa, Japan 1 A key benefit of the digital frequency control algorithm is wide capture range. To quantify the impact of the algorithm, the capture range is measured with and without the BBPD loop. When the BBPD loop is disabled, the ILO FRF can be set manually by a fixed DAC code. With 10Gb/s input data, the CDR is error free if the FRF is set within -2.6% and +3.2% of 5GHz (half rate). With the BBPD, the loop will correct to 5GHz if the initial FRF is set within -26% to +15% of 5GHz. Figure 10.4.4(a) shows the evaluated waveform in which the BBPD loop corrects an initial FRF of 3.68GHz to 5GHz for 10Gb/s operation. The loop response time is set by the loop gain, which can be adjusted digitally. For very fast locking, the
Takashi Masuda1, Ryota Shinoda1, Jeremy Chatwin2,