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ISSCC 2016Session 24 · ULTRA-EFFICIENT COMPUTING: APPLICATION-INSPIRED AND ANALOG-ASSISTED DIGITALAnalog Circuits65nm LP CMOS

A 36.8 2b-TOPS/W Self-Calibrating GPS Accelerator Implemented Using Analog Calculation in 65nm LP CMOS

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📋 论文概要

该论文提出一款用于GPS信号处理的自校准加速器,采用模拟计算技术实现高能效。在65nm LP CMOS工艺下,实现了36.8 2b-TOPS/W的能效,解决了传统数字处理能效低的问题。

💡 主要创新点

工艺节点
65nm LP CMOS
重要性
发表年份
ISSCC 2016

🏷 关键词

GPS加速器模拟计算自校准高能效

📄 原文摘要

Dennis Sylvester2, David Blaauw2, David Fick1, Michael B. Henry1 Isocline, Austin, TX, 2University of Michigan, Ann Arbor, MI 1 Many signal processing applications involve manipulating a large amount of data to generate a relatively narrow numerical result, such as, “does a particular object X exist in a picture?”, “which of several possible words was spoken in a sentence?”, or, “how strongly do these two patterns correlate?”. These applications take in noisy inputs with relatively low quantization, such as 8bits/color for video, or 8-bit audio samples, or 1b-to-2b digitized baseband signals. However, a sufficiently large amount of data allows noise rejection, and an accurate answer can be computed. This large-data-to-narrow-result property makes these applications a good fit for analog calculation, which also has limited resolution and inherent noise, but can offer higher energy efficiency than digital

👥 作者与机构

Skylar Skrzyniarz1,2, Laura Fick2, Jinal Shah2, Yejoong Kim2,

分类:Analog Circuits · 年份:ISSCC 2016