A 40Gb/s 14mW CMOS Wireline Receiver

📋 论文概要

该论文提出了一种采用极简设计方法的40Gb/s有线接收器，通过减少数据路径和时钟路径中的级数来降低功耗并提高带宽，实现了0.35mW/Gb/s的功率效率，显著优于传统接收器。

💡 主要创新点

• 采用极简主义设计，避免前端连续时间线性均衡器（CTLE）中的多级结构，减少功耗和带宽限制。
• 不使用正交振荡器，简化时钟路径以降低功耗。

🏷 关键词

📄 原文摘要

Reaching a power efficiency of 1mW/Gb/s has proven difficult for wireline transceivers operating at tens of gigabits per second. At 40Gb/s, recent receivers consume from 150mW [1] to 1W [2]. This paper describes a receiver that achieves a tenfold reduction in power and an efficiency of 0.35mW/Gb/s. The proposed receiver uses a “minimalist” approach, which recognizes that every additional stage in the data or clock path consumes more power and limits the bandwidth. The minimalist mentality avoids multiple stages in the front-end continuous-time linear equalizer (CTLE), quadrature oscillators in the clock and data recovery (CDR) circuit, clock or data buffers, or phase interpolation. Moreover, building blocks are shared among different functions so as to reduce the number of current paths between VDD and ground. Using charge-steering techniques extensively, the receiver contains only a few static bias currents adding

👥 作者与机构

Abishek Manian, Behzad Razavi

University of California, Los Angeles, CA