A 160MHz-BW 72dB-DR 40mW Continuous-Time ΔΣ Modulator in 16nm CMOS with Analog ISIReduction Technique

📋 论文概要

该论文提出了一种在16nm CMOS工艺下实现的连续时间ΔΣ调制器，用于LTE-A接收机的基带ADC，通过模拟ISI减少技术实现了160MHz带宽、72dB动态范围和40mW功耗，解决了高速率通信下带宽与功耗的矛盾。

💡 主要创新点

• 提出模拟ISI减少技术，有效降低连续时间ΔΣ调制器在高时钟速率下的符号间干扰，提升性能。
• 采用16nm先进CMOS工艺，结合电路优化，在160MHz带宽下实现72dB动态范围和仅40mW功耗，达到高能效。

🏷 关键词

📄 原文摘要

baseband ADC of an LTE-A receiver. To boost user throughput and increase network capacity, CT-DSMs will need to increase signal bandwidth (BW) while maintaining sufficient dynamic range (DR) and good power efficiency. For example, 5 downlink component carriers are no longer sufficient to meet the ITU requirement for IMT-advanced and up to 32 carriers and 640MHz RF bandwidth are under discussion for 3GPP Release 13. This increased BW drives CT-DSMs to operate at a several-GHz clock rate, but comes at a cost of higher power consumption, even when utilizing advanced nanometer CMOS technologies. Previous >100MHz-BW CT-DSMs required a 4GHz clock rate with oversampling-ratio (OSR) beyond 13× and power exceeding 250mW [1,2]. By contrast, the proposed CT-DSM decreases the OSR to 9× while consuming 40mW

👥 作者与机构

Su-Hao Wu, Tsung-Kai Kao, Zwei-Mei Lee, Ping Chen, Jui-Yuan Tsai

MediaTek, Hsinchu, Taiwan Continuous-time delta-sigma modulators (CT-DSMs) are well suited for the