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本文设计了一款40至64Gb/s的NRZ发射机，采用供电调节前端技术，在16nm FinFET工艺下实现高速数据传输，旨在满足数据中心和电信基础设施对更高带宽的需求，同时保持功耗不变。
Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang Xilinx, San Jose, CA Due to increasing bandwidth demand in data centers and telecommunication infrastructures, the maximum data-rate of wireline transceivers is projected to double from 32Gb/s to 64Gb/s while keeping the same power envelope. This paper presents the design of a 64Gb/s NRZ transmitter for short-reach electrical links in a 16nm FinFET process. It is applicable to standards such as CEI-56-VSR/MR, using power efficient techniques that take into considerations FinFET device properties: low DIBL, negligible body effect, low junction capacitance, low channel leakage, high intrinsic gain, high gate capacitance and resistance, high flicker noise, and steep CV curve in accumulation region. Quad-rate architecture (Fig. 3.7.1) is chosen to relax serialization timing [1]. The transmitter uses 3-tap pre-emphasis (one pre, main and post tap) to equalize the
Yohan Frans, Scott McLeod, Hiva Hedayati, Mohamed Elzeftawi,