An Oversampling SAR ADC with DAC Mismatch Error Shaping Achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS

📋 论文概要

该论文提出了一种过采样SAR ADC，采用DAC失配误差整形技术，有效抑制了电容失配引起的非线性。在55nm CMOS工艺中实现了105dB SFDR和101dB SNDR，带宽为1kHz，解决了高精度低速传感器接口中SAR ADC的非线性和噪声问题。

💡 主要创新点

• 提出了DAC失配误差整形技术，将失配噪声整形到高频，从而在低频带内获得高线性度。
• 结合过采样和误差整形，在不增加功耗的前提下大幅提升了SAR ADC的动态范围和SFDR。

🏷 关键词

📄 原文摘要

The successive-approximation-register (SAR) architecture is well-known for its high power efficiency in medium-resolution A/D conversions. Together with time interleaving, it can challenge the regime of flash ADCs in high-speed, lowresolution applications [1]. However, when considered for high-precision, low-speed sensor readout interfaces, SAR ADCs suffer from nonlinearity resulting from capacitor mismatch and limited dynamic range due to comparator noise. Previous works [2-3] adopt oversampling to shift noise and nonlinearity into high frequencies. Dithering and chopping are used in [2] to modulate harmonic distortion and flicker noise out of signal bandwidth, achieving an in-band SFDR of 87.1dB and an SNDR of 79.1dB along with data-driven noise reduction. Noise shaping proposed in [3] suppresses the in-band noise around 10dB at a low oversampling ratio (OSR) of 4 with no linearity improvement. DAC nonlinearity

👥 作者与机构

Yun-Shiang Shu, Liang-Ting Kuo, Tien-Yu Lo

MediaTek, Hsinchu, Taiwan