A 0.5-to-9.5GHz 1.2µs-Lock-Time Fractional-N DPLL with ±1.25% UI Period Jitter in 16nm CMOS For Dynamic Frequency and Core-Count Scaling in SoC

📋 论文概要

本文提出了一款应用于动态频率和核心计数值缩放的分数-N数字锁相环(DPLL)，覆盖0.5至9.5GHz频率范围，锁定时间仅1.2µs，周期抖动为±1.25% UI，采用16nm CMOS工艺制造。该设计解决了SoC在动态频率缩放和核心快速上电过程中对快速锁定、无频率过冲及宽频率范围的需求。

💡 主要创新点

• 实现超快锁定时间1.2µs，支持动态频率缩放和核心快速上电重启而无需中断。
• 通过数字架构和算法优化，在宽频率范围（0.5-9.5GHz）内保持低周期抖动（±1.25% UI）。

🏷 关键词

📄 原文摘要

incorporate power management techniques such as dynamic frequency scaling (DFS), which dynamically changes operating frequencies, and dynamic core-count scaling (DCCS), which rapidly power cycles the cores between active and idle states. For digital clocking in such SoCs, the PLL needs to support rapid frequency change and fast locking, both without frequency overshoot, so that SoCs can continue operation without interruption during DFS and start operation right after PLL reset is released during DCCS. Moreover, digital clocking PLLs are also required to have a wide frequency range, low period jitter (JP) and low power. Conventional PLLs like [1] use coarse and fine frequency tuning to achieve both low JP, as well as wide frequency range, but may produce frequency overshoots during initial

👥 作者与机构

Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su,

Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori Broadcom, Irvine, CA Today’s multicore processors and complex multimedia SoCs