A 0.076mm2 12b 26.5mW 600MS/s 4×-Interleaved Subranging SAR-ΔΣ ADC with On-Chip Buffer in 28nm CMOS switch, is parasitic sensitive. Scaling of the LSB capacitance is therefore dictated by the parasitic capacitance of a minimum size switch instead of kT/C noise requirements. In deep-submicron technologies, this usually leads to a significantly larger core area with respect to a CR-DAC.

📋 论文概要

本文提出了一种4路交织的亚区SAR-ΔΣ ADC，采用分段SAR-DAC架构（CS-DAC用于4位MSB，CR-DAC用于6位LSB），在28nm CMOS工艺中实现了0.076mm²的小面积和26.5mW的低功耗，解决了传统SAR ADC面积大、对参考噪声敏感的问题。

💡 主要创新点

• 采用分段SAR-DAC架构，结合电流定标DAC（CS-DAC）和电荷重分配DAC（CR-DAC），在保持线性度的同时显著减小了核心电容面积。

📄 原文摘要

competitive core area a segmented SAR-DAC architecture is adopted using a CSDAC for the 4 MSBs and a CR-DAC for the remaining 6 LSBs (Fig. 27.8.2). The parasitic insensitive 6 LSBs can be scaled down as in a conventional CR-DAC, while the switch parasitics in the 4 MSBs CS-DAC are a small portion of the capacitances and do not impact linearity. As the CR-DAC is limited to the LSBs, the sensitivity to reference noise/ripple is small. In this way, each lane SAR-DAC core capacitor of 300fF requires a reference capacitor of only 5pF. Marvell, Pavia, Italy Integration of low-power and area-efficient ADCs is a key differentiator in modern mixed-signal SoCs. In scaled technologies, power challenges have been addressed using SAR architectures, often in combination with techniques like redundancy, asynchronous operation, and time interleaving to meet the application sampling rate requirements. However, for high-resolution ADCs (9b+

👥 作者与机构

Alessandro Venca, Nicola Ghittori, Alessandro Bosi, Claudio Nani, To exploit the CS-DAC area advantage in the reference design while keeping